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[Qemu-devel] [PATCH v6 4/9] i386: Add new property to control cache info
From: |
Babu Moger |
Subject: |
[Qemu-devel] [PATCH v6 4/9] i386: Add new property to control cache info |
Date: |
Tue, 10 Apr 2018 19:16:04 -0400 |
This will be used to control the cache information.
By default new information will be displayed. If user
passes "-cpu legacy-cache" then older information will
be displayed even if the hardware supports new information.
It will be "on" for machine type "pc-q35-2.10" for compatibility.
Signed-off-by: Babu Moger <address@hidden>
Tested-by: Geoffrey McRae <address@hidden>
---
include/hw/i386/pc.h | 4 ++++
target/i386/cpu.c | 1 +
target/i386/cpu.h | 5 +++++
3 files changed, 10 insertions(+)
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index ffee841..d904a3c 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -327,6 +327,10 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
.driver = "q35-pcihost",\
.property = "x-pci-hole64-fix",\
.value = "off",\
+ },{\
+ .driver = TYPE_X86_CPU,\
+ .property = "legacy-cache",\
+ .value = "on",\
},
#define PC_COMPAT_2_9 \
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 3b2a19a..1659320 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -5129,6 +5129,7 @@ static Property x86_cpu_properties[] = {
false),
DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
+ DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, false),
/*
* From "Requirements for Implementing the Microsoft
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index aff8396..fe8edf6 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1394,6 +1394,11 @@ struct X86CPU {
*/
bool enable_l3_cache;
+ /* Compatibility bits for old machine types.
+ * If true present the old cache topology information
+ */
+ bool legacy_cache;
+
/* Compatibility bits for old machine types: */
bool enable_cpuid_0xb;
--
1.8.3.1
- [Qemu-devel] [PATCH v6 0/9] i386: Enable TOPOEXT to support hyperthreading on AMD CPU, Babu Moger, 2018/04/10
- [Qemu-devel] [PATCH v6 2/9] i386: Add cache information in X86CPUDefinition, Babu Moger, 2018/04/10
- [Qemu-devel] [PATCH v6 1/9] i386: Helpers to encode cache information consistently, Babu Moger, 2018/04/10
- [Qemu-devel] [PATCH v6 4/9] i386: Add new property to control cache info,
Babu Moger <=
- [Qemu-devel] [PATCH v6 3/9] i386: Initialize cache information for EPYC family processors, Babu Moger, 2018/04/10
- [Qemu-devel] [PATCH v6 5/9] i386: Use the statically loaded cache definitions, Babu Moger, 2018/04/10
- [Qemu-devel] [PATCH v6 6/9] i386: Populate AMD Processor Cache Information for cpuid 0x8000001D, Babu Moger, 2018/04/10
- [Qemu-devel] [PATCH v6 8/9] i386: Enable TOPOEXT feature on AMD EPYC CPU, Babu Moger, 2018/04/10
- [Qemu-devel] [PATCH v6 9/9] i386: Remove generic SMT thread check, Babu Moger, 2018/04/10
- [Qemu-devel] [PATCH v6 7/9] i386: Add support for CPUID_8000_001E for AMD, Babu Moger, 2018/04/10