Re: [Qemu-devel] [PATCH v3 05/12] hw/pci: introduce PCISVAOps to PCIDevice

[David Gibson]

On Tue, Mar 06, 2018 at 06:33:52PM +0800, Liu, Yi L wrote:
> On Mon, Mar 05, 2018 at 02:31:44PM +1100, David Gibson wrote:
> > On Thu, Mar 01, 2018 at 06:31:55PM +0800, Liu, Yi L wrote:
> > > This patch intoduces PCISVAOps for virt-SVA.
> > >
> > > So far, to setup virt-SVA for assigned SVA capable device, needs to
> > > config host translation structures. e.g. for VT-d, needs to set the
> > > guest pasid table to host and enable nested translation. Besides,
> > > vIOMMU emulator needs to forward guest's cache invalidation to host.
> > > On VT-d, it is guest's invalidation to 1st level translation related
> > > cache, such invalidation should be forwarded to host.
> > >
> > > Proposed PCISVAOps are:
> > > * sva_bind_guest_pasid_table: set the guest pasid table to host, and
> > >                               enable nested translation in host
> > > * sva_register_notifier: register sva_notifier to forward guest's
> > >                          cache invalidation to host
> > > * sva_unregister_notifier: unregister sva_notifier
> > >
> > > The PCISVAOps should be provided by vfio or modules alike. Mainly for
> > > assigned SVA capable devices.
> > >
> > > Take virt-SVA on VT-d as an exmaple:
> > > If a guest wants to setup virt-SVA for an assigned SVA capable device,
> > > it programs its context entry. vIOMMU emulator captures guest's context
> > > entry programming, and figure out the target device. vIOMMU emulator
> > > use the pci_device_sva_bind_pasid_table() API to bind the guest pasid
> > > table to host.
> > >
> > > Guest would also program its pasid table. vIOMMU emulator captures
> > > guest's pasid entry programming. In Qemu, needs to allocate an
> > > AddressSpace to stand for the pasid tagged address space and Qemu also
> > > needs to register sva_notifier to forward future cache invalidation
> > > request to host.
> > >
> > > Allocating AddressSpace to stand for the pasid tagged address space is
> > > for the emulation of emulated SVA capable devices. Emulated SVA capable
> > > devices may issue SVA aware DMAs, Qemu needs to emulate read/write to a
> > > pasid tagged AddressSpace. Thus needs an abstraction for such address
> > > space in Qemu.
> > >
> > > Signed-off-by: Liu, Yi L <address@hidden>
> >
> > So PCISVAOps is roughly equivalent to the cluster-of-PASIDs context I
> > was suggesting in my earlier comments,
> 
> yes, it is. The purpose is to expose pasid table bind and sva notfier
> registration/unregistration to vIOMMU emulators.
> 
> > however it's only an ops
> > structure.  That means you can't easily share a context between
> > multiple PCI devices which is unfortunate because:
> >     * The simplest use case for SVA I can see would just put the
> >       same set of PASIDs into place for every SVA capable device
> 
> Do you mean for emulated SVA capable device?

Not necessarily.  I'd expect that model could be useful for both
emulated and passthrough SVA capable devices.

> >     * Sometimes the IOMMU can't determine exactly what device a DMA
> >       came from.  Now the bridge cases where this applies are probably
> >       unlikely with SVA devices, but I wouldn't want to bet on it.  In
> >       addition, the chances some manufacturer will eventually put out
> >       a buggy multifunction SVA capable device that use the wrong RIDs
> >       for the secondary functions is pretty darn high.
> 
> I'm not sure I 100% got your point here. Do yu mean physical device?
> In PCIE TLP, DMA packet should have a RID field?

Yes, but that RID isn't accurate in all cases.

One case is if you have a PCIe device behind both a PCIe->PCI and
PCI->PCIe bridge.  Now obviously SVA won't work in that case, but it
would be good to at least detect it and refuse to attempt SVA.

Another case is with a buggy device that just sends the wrong RID.  In
particular there are some multifunction devices that use function 0's
RID for all functions.  Obviously that's a hardware bug and we can't
expect everything to work in this case.  But forcing all the functions
to share an SVAContext in this case - like we alreayd force them to
share an IOMMU group - allows us to reason about what will and won't work

> And it looks more like
> a hardware layer trouble. For this series, it only provides necessary
> software support to make sure guest's SVA operation is well prepared
> before the SVA device issues the SVA aware DMA. e.g. link guest's pasid
> table to host, and config iommu translation in nested mode.
> 
> >
> > So I think instead you want a cluster-of-PASIDs object which has an
> > ops table including both these and the per-PASID calls from the
> > earlier patches (but the per-PASID calls would now take an explicit
> > PASID value).
> 
> I didn't quite get "including both these and the per-PASID calls".
> What do you mean by "these"? Do you mean the PCISVAOps?

I mean that I think PCISVAOps should become a full object including an
ops table, not just an ops table.  That table would include the things
currently in PCISVAOps.  It would also include callbacks for the
things that are in your per-PASID object in this draft, but those
callbacks would now need to take an explicit PASIC parameter.

-- 
David Gibson                    | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
                                | _way_ _around_!
http://www.ozlabs.org/~dgibson

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