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[Qemu-devel] [PATCH v1 5/5] target-microblaze: mmu: Make the TLBX MISS b
From: |
Edgar E. Iglesias |
Subject: |
[Qemu-devel] [PATCH v1 5/5] target-microblaze: mmu: Make the TLBX MISS bit read-only |
Date: |
Thu, 19 Apr 2018 13:21:31 +0200 |
From: "Edgar E. Iglesias" <address@hidden>
Make the TLBX MISS bit read-only.
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
target/microblaze/mmu.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c
index 8391811900..9d5e6aa8a5 100644
--- a/target/microblaze/mmu.c
+++ b/target/microblaze/mmu.c
@@ -273,6 +273,10 @@ void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
env->mmu.regs[rn] = v;
}
break;
+ case MMU_R_TLBX:
+ /* Bit 31 is read-only. */
+ env->mmu.regs[rn] = deposit32(env->mmu.regs[rn], 0, 31, v);
+ break;
case MMU_R_TLBSX:
{
struct microblaze_mmu_lookup lu;
--
2.14.1
- [Qemu-devel] [PATCH v1 1/5] target-microblaze: Respect MSR.PVR as read-only, (continued)
[Qemu-devel] [PATCH v1 3/5] target-microblaze: Don't clobber the IMM reg for ld/st reversed, Edgar E. Iglesias, 2018/04/19
[Qemu-devel] [PATCH v1 4/5] target-microblaze: mmu: Make TLBSX write-only, Edgar E. Iglesias, 2018/04/19
[Qemu-devel] [PATCH v1 2/5] target-microblaze: Fix trap checks for FPU insns, Edgar E. Iglesias, 2018/04/19
[Qemu-devel] [PATCH v1 5/5] target-microblaze: mmu: Make the TLBX MISS bit read-only,
Edgar E. Iglesias <=