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[Qemu-devel] [PATCH v8 03/35] RISC-V: Use ROM base address and size from
From: |
Michael Clark |
Subject: |
[Qemu-devel] [PATCH v8 03/35] RISC-V: Use ROM base address and size from memmap |
Date: |
Thu, 26 Apr 2018 11:45:06 +1200 |
Another case of replacing hard coded constants, this time
referring to the definition in the virt machine's memmap.
Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
---
hw/riscv/virt.c | 4 ++--
include/hw/riscv/virt.h | 2 --
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index dc74fd6..ac0106e 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -341,11 +341,11 @@ static void riscv_virt_board_init(MachineState *machine)
};
/* copy in the reset vector */
- copy_le32_to_phys(ROM_BASE, reset_vec, sizeof(reset_vec));
+ copy_le32_to_phys(memmap[VIRT_MROM].base, reset_vec, sizeof(reset_vec));
/* copy in the device tree */
qemu_fdt_dumpdtb(s->fdt, s->fdt_size);
- cpu_physical_memory_write(ROM_BASE + sizeof(reset_vec),
+ cpu_physical_memory_write(memmap[VIRT_MROM].base + sizeof(reset_vec),
s->fdt, s->fdt_size);
/* create PLIC hart topology configuration string */
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 2fbe808..655e85d 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -23,8 +23,6 @@
#define VIRT(obj) \
OBJECT_CHECK(RISCVVirtState, (obj), TYPE_RISCV_VIRT_BOARD)
-enum { ROM_BASE = 0x1000 };
-
typedef struct {
/*< private >*/
SysBusDevice parent_obj;
--
2.7.0
- [Qemu-devel] [PATCH v8 00/35] QEMU 2.13 Privileged ISA emulation updates, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 01/35] RISC-V: Replace hardcoded constants with enum values, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 02/35] RISC-V: Make virt board description match spike, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 03/35] RISC-V: Use ROM base address and size from memmap,
Michael Clark <=
- [Qemu-devel] [PATCH v8 04/35] RISC-V: Remove identity_translate from load_elf, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 05/35] RISC-V: Remove unused class definitions, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 06/35] RISC-V: Include instruction hex in disassembly, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 07/35] RISC-V: Make some header guards more specific, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 08/35] RISC-V: Make virt header comment title consistent, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 09/35] RISC-V: Remove EM_RISCV ELF_MACHINE indirection, Michael Clark, 2018/04/25