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[Qemu-devel] [PATCH v8 25/35] RISC-V: Move non-ops from op_helper to cpu
From: |
Michael Clark |
Subject: |
[Qemu-devel] [PATCH v8 25/35] RISC-V: Move non-ops from op_helper to cpu_helper |
Date: |
Thu, 26 Apr 2018 11:45:28 +1200 |
This patch makes op_helper.c contain only instruction
operation helpers used by translate.c and moves any
unrelated cpu helpers into cpu_helper.c. No logic is
changed by this patch.
Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Cc: Palmer Dabbelt <address@hidden>
Cc: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
---
target/riscv/Makefile.objs | 2 +-
target/riscv/{helper.c => cpu_helper.c} | 34 ++++++++++++++++++++++++++++++++-
target/riscv/op_helper.c | 33 --------------------------------
3 files changed, 34 insertions(+), 35 deletions(-)
rename target/riscv/{helper.c => cpu_helper.c} (95%)
diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
index abd0a7c..fcc5d34 100644
--- a/target/riscv/Makefile.objs
+++ b/target/riscv/Makefile.objs
@@ -1 +1 @@
-obj-y += translate.o op_helper.o helper.o cpu.o fpu_helper.o gdbstub.o pmp.o
+obj-y += translate.o op_helper.o cpu_helper.o cpu.o fpu_helper.o gdbstub.o
pmp.o
diff --git a/target/riscv/helper.c b/target/riscv/cpu_helper.c
similarity index 95%
rename from target/riscv/helper.c
rename to target/riscv/cpu_helper.c
index 47d116e..fb3f7ef 100644
--- a/target/riscv/helper.c
+++ b/target/riscv/cpu_helper.c
@@ -1,5 +1,5 @@
/*
- * RISC-V emulation helpers for qemu.
+ * RISC-V CPU helpers for qemu.
*
* Copyright (c) 2016-2017 Sagar Karandikar, address@hidden
* Copyright (c) 2017-2018 SiFive, Inc.
@@ -72,6 +72,38 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int
interrupt_request)
#if !defined(CONFIG_USER_ONLY)
+/* iothread_mutex must be held */
+uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
+{
+ CPURISCVState *env = &cpu->env;
+ uint32_t old_mip, new_mip;
+
+ do {
+ old_mip = atomic_read(&env->mip);
+ new_mip = (old_mip & ~mask) | (value & mask);
+ } while (atomic_cmpxchg(&env->mip, old_mip, new_mip) != old_mip);
+
+ if (new_mip && !old_mip) {
+ cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
+ } else if (!new_mip && old_mip) {
+ cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
+ }
+
+ return old_mip;
+}
+
+void riscv_set_mode(CPURISCVState *env, target_ulong newpriv)
+{
+ if (newpriv > PRV_M) {
+ g_assert_not_reached();
+ }
+ if (newpriv == PRV_H) {
+ newpriv = PRV_U;
+ }
+ /* tlb_flush is unnecessary as mode is contained in mmu_idx */
+ env->priv = newpriv;
+}
+
/* get_physical_address - get the physical address for this virtual address
*
* Do a page table walk to obtain the physical address corresponding to a
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 2a7f045..4b4d62b 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -640,38 +640,6 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong
src,
#ifndef CONFIG_USER_ONLY
-/* iothread_mutex must be held */
-uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
-{
- CPURISCVState *env = &cpu->env;
- uint32_t old_mip, new_mip;
-
- do {
- old_mip = atomic_read(&env->mip);
- new_mip = (old_mip & ~mask) | (value & mask);
- } while (atomic_cmpxchg(&env->mip, old_mip, new_mip) != old_mip);
-
- if (new_mip && !old_mip) {
- cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
- } else if (!new_mip && old_mip) {
- cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
- }
-
- return old_mip;
-}
-
-void riscv_set_mode(CPURISCVState *env, target_ulong newpriv)
-{
- if (newpriv > PRV_M) {
- g_assert_not_reached();
- }
- if (newpriv == PRV_H) {
- newpriv = PRV_U;
- }
- /* tlb_flush is unnecessary as mode is contained in mmu_idx */
- env->priv = newpriv;
-}
-
target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
{
if (!(env->priv >= PRV_S)) {
@@ -722,7 +690,6 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong
cpu_pc_deb)
return retpc;
}
-
void helper_wfi(CPURISCVState *env)
{
CPUState *cs = CPU(riscv_env_get_cpu(env));
--
2.7.0
- Re: [Qemu-devel] [PATCH v8 16/35] RISC-V: Make mtvec/stvec ignore vectored traps, (continued)
- [Qemu-devel] [PATCH v8 17/35] RISC-V: No traps on writes to misa, minstret, mcycle, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 18/35] RISC-V: Clear mtval/stval on exceptions without info, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 19/35] RISC-V: Allow S-mode mxr access when priv ISA >= v1.10, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 20/35] RISC-V: Use [ms]counteren CSRs when priv ISA >= v1.10, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 21/35] RISC-V: Add mcycle/minstret support for -icount auto, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 22/35] RISC-V: Use atomic_cmpxchg to update PLIC bitmaps, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 23/35] RISC-V: Simplify riscv_cpu_local_irqs_pending, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 24/35] RISC-V: Allow setting and clearing multiple irqs, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 25/35] RISC-V: Move non-ops from op_helper to cpu_helper,
Michael Clark <=
- [Qemu-devel] [PATCH v8 26/35] RISC-V: Update CSR and interrupt definitions, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 28/35] RISC-V: Implement atomic mip/sip CSR updates, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 27/35] RISC-V: Implement modular CSR helper interface, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 29/35] RISC-V: Implement existential predicates for CSRs, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 30/35] RISC-V: Split out mstatus_fs from tb_flags, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 31/35] RISC-V: Mark mstatus.fs dirty, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 32/35] RISC-V: Implement mstatus.TSR/TW/TVM, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 33/35] RISC-V: Add public API for the CSR dispatch table, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 34/35] RISC-V: Add hartid and \n to interrupt logging, Michael Clark, 2018/04/25