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Re: [Qemu-devel] [PATCH v8 09/35] RISC-V: Remove EM_RISCV ELF_MACHINE in
From: |
Alistair Francis |
Subject: |
Re: [Qemu-devel] [PATCH v8 09/35] RISC-V: Remove EM_RISCV ELF_MACHINE indirection |
Date: |
Thu, 26 Apr 2018 16:42:36 +0000 |
On Wed, Apr 25, 2018 at 4:51 PM Michael Clark <address@hidden> wrote:
> Pointless indirection. Other ports use EM_ constants directly.
> Cc: Sagar Karandikar <address@hidden>
> Cc: Bastian Koppelmann <address@hidden>
> Signed-off-by: Michael Clark <address@hidden>
> Signed-off-by: Palmer Dabbelt <address@hidden>
> Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Alistair
> ---
> hw/riscv/sifive_e.c | 2 +-
> hw/riscv/sifive_u.c | 2 +-
> hw/riscv/spike.c | 2 +-
> hw/riscv/virt.c | 2 +-
> target/riscv/cpu.h | 1 -
> 5 files changed, 4 insertions(+), 5 deletions(-)
> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> index 4872b68..39e4cb4 100644
> --- a/hw/riscv/sifive_e.c
> +++ b/hw/riscv/sifive_e.c
> @@ -88,7 +88,7 @@ static uint64_t load_kernel(const char *kernel_filename)
> if (load_elf(kernel_filename, NULL, NULL,
> &kernel_entry, NULL, &kernel_high,
> - 0, ELF_MACHINE, 1, 0) < 0) {
> + 0, EM_RISCV, 1, 0) < 0) {
> error_report("qemu: could not load kernel '%s'",
kernel_filename);
> exit(1);
> }
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 2412b5d..115618b 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -74,7 +74,7 @@ static uint64_t load_kernel(const char *kernel_filename)
> if (load_elf(kernel_filename, NULL, NULL,
> &kernel_entry, NULL, &kernel_high,
> - 0, ELF_MACHINE, 1, 0) < 0) {
> + 0, EM_RISCV, 1, 0) < 0) {
> error_report("qemu: could not load kernel '%s'",
kernel_filename);
> exit(1);
> }
> diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
> index f370f12..3f6bd0a 100644
> --- a/hw/riscv/spike.c
> +++ b/hw/riscv/spike.c
> @@ -64,7 +64,7 @@ static uint64_t load_kernel(const char *kernel_filename)
> uint64_t kernel_entry, kernel_high;
> if (load_elf_ram_sym(kernel_filename, NULL, NULL,
> - &kernel_entry, NULL, &kernel_high, 0, ELF_MACHINE, 1, 0,
> + &kernel_entry, NULL, &kernel_high, 0, EM_RISCV, 1, 0,
> NULL, true, htif_symbol_callback) < 0) {
> error_report("qemu: could not load kernel '%s'",
kernel_filename);
> exit(1);
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 782996c..090befe 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -68,7 +68,7 @@ static uint64_t load_kernel(const char *kernel_filename)
> if (load_elf(kernel_filename, NULL, NULL,
> &kernel_entry, NULL, &kernel_high,
> - 0, ELF_MACHINE, 1, 0) < 0) {
> + 0, EM_RISCV, 1, 0) < 0) {
> error_report("qemu: could not load kernel '%s'",
kernel_filename);
> exit(1);
> }
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 41e06ac..9871e6f 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -34,7 +34,6 @@
> #define TCG_GUEST_DEFAULT_MO 0
> -#define ELF_MACHINE EM_RISCV
> #define CPUArchState struct CPURISCVState
> #include "qemu-common.h"
> --
> 2.7.0
- [Qemu-devel] [PATCH v8 03/35] RISC-V: Use ROM base address and size from memmap, (continued)
- [Qemu-devel] [PATCH v8 03/35] RISC-V: Use ROM base address and size from memmap, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 04/35] RISC-V: Remove identity_translate from load_elf, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 05/35] RISC-V: Remove unused class definitions, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 06/35] RISC-V: Include instruction hex in disassembly, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 07/35] RISC-V: Make some header guards more specific, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 08/35] RISC-V: Make virt header comment title consistent, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 09/35] RISC-V: Remove EM_RISCV ELF_MACHINE indirection, Michael Clark, 2018/04/25
- Re: [Qemu-devel] [PATCH v8 09/35] RISC-V: Remove EM_RISCV ELF_MACHINE indirection,
Alistair Francis <=
- [Qemu-devel] [PATCH v8 10/35] RISC-V: Remove erroneous comment from translate.c, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 12/35] RISC-V: Update address bits to support sv39 and sv48, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 11/35] RISC-V: Mark ROM read-only after copying in code, Michael Clark, 2018/04/25
[Qemu-devel] [PATCH v8 13/35] RISC-V: Improve page table walker spec compliance, Michael Clark, 2018/04/25