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[Qemu-devel] [PULL v1 1/5] target-microblaze: Respect MSR.PVR as read-on
From: |
Edgar E. Iglesias |
Subject: |
[Qemu-devel] [PULL v1 1/5] target-microblaze: Respect MSR.PVR as read-only |
Date: |
Mon, 30 Apr 2018 17:08:33 +0200 |
From: "Edgar E. Iglesias" <address@hidden>
Respect MSR.PVR as read-only. We were wrongly overwriting the PVR bit.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
target/microblaze/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 7628b0e25b..f739751930 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -424,7 +424,7 @@ static inline void msr_write(DisasContext *dc, TCGv v)
/* PVR bit is not writable. */
tcg_gen_andi_tl(t, v, ~MSR_PVR);
tcg_gen_andi_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], MSR_PVR);
- tcg_gen_or_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], v);
+ tcg_gen_or_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t);
tcg_temp_free(t);
}
--
2.14.1
- [Qemu-devel] [PULL v1 0/5] Xilinx queue 2018-04-30, Edgar E. Iglesias, 2018/04/30
- [Qemu-devel] [PULL v1 1/5] target-microblaze: Respect MSR.PVR as read-only,
Edgar E. Iglesias <=
- [Qemu-devel] [PULL v1 2/5] target-microblaze: Fix trap checks for FPU insns, Edgar E. Iglesias, 2018/04/30
- [Qemu-devel] [PULL v1 3/5] target-microblaze: Don't clobber the IMM reg for ld/st reversed, Edgar E. Iglesias, 2018/04/30
- [Qemu-devel] [PULL v1 4/5] target-microblaze: mmu: Make TLBSX write-only, Edgar E. Iglesias, 2018/04/30
- [Qemu-devel] [PULL v1 5/5] target-microblaze: mmu: Make the TLBX MISS bit read-only, Edgar E. Iglesias, 2018/04/30
- Re: [Qemu-devel] [PULL v1 0/5] Xilinx queue 2018-04-30, Peter Maydell, 2018/04/30