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Re: [Qemu-devel] [PATCH v2 14/36] target-microblaze: Name special regist
From: |
Alistair Francis |
Subject: |
Re: [Qemu-devel] [PATCH v2 14/36] target-microblaze: Name special registers we support |
Date: |
Wed, 9 May 2018 13:57:34 -0700 |
On Tue, May 8, 2018 at 10:31 AM, Edgar E. Iglesias
<address@hidden> wrote:
> From: "Edgar E. Iglesias" <address@hidden>
>
> Name special registers we support.
>
> Signed-off-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Alistair
> ---
> target/microblaze/translate.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
> index c971fe3b72..6cc92d09c9 100644
> --- a/target/microblaze/translate.c
> +++ b/target/microblaze/translate.c
> @@ -105,8 +105,8 @@ static const char *regnames[] =
>
> static const char *special_regnames[] =
> {
> - "rpc", "rmsr", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
> - "sr8", "sr9", "sr10", "sr11", "sr12", "sr13"
> + "rpc", "rmsr", "sr2", "rear", "sr4", "resr", "sr6", "rfsr",
> + "sr8", "sr9", "sr10", "rbtr", "sr12", "redr"
> };
>
> static inline void t_sync_flags(DisasContext *dc)
> --
> 2.14.1
>
>
- [Qemu-devel] [PATCH v2 06/36] target-microblaze: Correct the PVR array size, (continued)
- [Qemu-devel] [PATCH v2 06/36] target-microblaze: Correct the PVR array size, Edgar E. Iglesias, 2018/05/08
- [Qemu-devel] [PATCH v2 09/36] target-microblaze: Conditionalize setting of PVR11_USE_MMU, Edgar E. Iglesias, 2018/05/08
- [Qemu-devel] [PATCH v2 10/36] target-microblaze: Bypass MMU with MMU_NOMMU_IDX, Edgar E. Iglesias, 2018/05/08
- [Qemu-devel] [PATCH v2 08/36] target-microblaze: Remove USE_MMU PVR checks, Edgar E. Iglesias, 2018/05/08
- [Qemu-devel] [PATCH v2 11/36] target-microblaze: Make compute_ldst_addr always use a temp, Edgar E. Iglesias, 2018/05/08
- [Qemu-devel] [PATCH v2 07/36] target-microblaze: Tighten up TCGv_i32 vs TCGv type usage, Edgar E. Iglesias, 2018/05/08
- [Qemu-devel] [PATCH v2 12/36] target-microblaze: Remove pointer indirection for ld/st addresses, Edgar E. Iglesias, 2018/05/08
- [Qemu-devel] [PATCH v2 14/36] target-microblaze: Name special registers we support, Edgar E. Iglesias, 2018/05/08
- Re: [Qemu-devel] [PATCH v2 14/36] target-microblaze: Name special registers we support,
Alistair Francis <=
- [Qemu-devel] [PATCH v2 13/36] target-microblaze: Use TCGv for load/store addresses, Edgar E. Iglesias, 2018/05/08
- [Qemu-devel] [PATCH v2 17/36] target-microblaze: dec_msr: Use bool and extract32, Edgar E. Iglesias, 2018/05/08
- [Qemu-devel] [PATCH v2 15/36] target-microblaze: Break out trap_userspace(), Edgar E. Iglesias, 2018/05/08
- [Qemu-devel] [PATCH v2 16/36] target-microblaze: Break out trap_illegal(), Edgar E. Iglesias, 2018/05/08
- [Qemu-devel] [PATCH v2 18/36] target-microblaze: dec_msr: Reuse more code when reg-decoding, Edgar E. Iglesias, 2018/05/08
- [Qemu-devel] [PATCH v2 19/36] target-microblaze: dec_msr: Fix MTS to FSR, Edgar E. Iglesias, 2018/05/08
- [Qemu-devel] [PATCH v2 21/36] target-microblaze: Setup for 64bit addressing, Edgar E. Iglesias, 2018/05/08
- [Qemu-devel] [PATCH v2 23/36] target-microblaze: Implement MFSE EAR, Edgar E. Iglesias, 2018/05/08
- [Qemu-devel] [PATCH v2 20/36] target-microblaze: Make special registers 64-bit, Edgar E. Iglesias, 2018/05/08