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[Qemu-devel] [PULL 15/21] target/arm: Fill in disas_ldst_atomic
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 15/21] target/arm: Fill in disas_ldst_atomic |
Date: |
Thu, 10 May 2018 18:45:13 +0100 |
From: Richard Henderson <address@hidden>
This implements all of the v8.1-Atomics instructions except
for compare-and-swap, which is decoded elsewhere.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/translate-a64.c | 38 ++++++++++++++++++++++++++++++++++++--
1 file changed, 36 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index bb8a176f9a..86989fda6c 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -84,6 +84,7 @@ typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64);
typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);
typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
+typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, TCGMemOp);
/* Note that the gvec expanders operate on offsets + sizes. */
typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t);
@@ -2772,6 +2773,8 @@ static void disas_ldst_atomic(DisasContext *s, uint32_t
insn,
int rn = extract32(insn, 5, 5);
int o3_opc = extract32(insn, 12, 4);
int feature = ARM_FEATURE_V8_ATOMICS;
+ TCGv_i64 tcg_rn, tcg_rs;
+ AtomicThreeOpFn *fn;
if (is_vector) {
unallocated_encoding(s);
@@ -2779,14 +2782,32 @@ static void disas_ldst_atomic(DisasContext *s, uint32_t
insn,
}
switch (o3_opc) {
case 000: /* LDADD */
+ fn = tcg_gen_atomic_fetch_add_i64;
+ break;
case 001: /* LDCLR */
+ fn = tcg_gen_atomic_fetch_and_i64;
+ break;
case 002: /* LDEOR */
+ fn = tcg_gen_atomic_fetch_xor_i64;
+ break;
case 003: /* LDSET */
+ fn = tcg_gen_atomic_fetch_or_i64;
+ break;
case 004: /* LDSMAX */
+ fn = tcg_gen_atomic_fetch_smax_i64;
+ break;
case 005: /* LDSMIN */
+ fn = tcg_gen_atomic_fetch_smin_i64;
+ break;
case 006: /* LDUMAX */
+ fn = tcg_gen_atomic_fetch_umax_i64;
+ break;
case 007: /* LDUMIN */
+ fn = tcg_gen_atomic_fetch_umin_i64;
+ break;
case 010: /* SWP */
+ fn = tcg_gen_atomic_xchg_i64;
+ break;
default:
unallocated_encoding(s);
return;
@@ -2796,8 +2817,21 @@ static void disas_ldst_atomic(DisasContext *s, uint32_t
insn,
return;
}
- (void)rs;
- (void)rn;
+ if (rn == 31) {
+ gen_check_sp_alignment(s);
+ }
+ tcg_rn = cpu_reg_sp(s, rn);
+ tcg_rs = read_cpu_reg(s, rs, true);
+
+ if (o3_opc == 1) { /* LDCLR */
+ tcg_gen_not_i64(tcg_rs, tcg_rs);
+ }
+
+ /* The tcg atomic primitives are all full barriers. Therefore we
+ * can ignore the Acquire and Release bits of this instruction.
+ */
+ fn(cpu_reg(s, rt), tcg_rn, tcg_rs, get_mem_index(s),
+ s->be_data | size | MO_ALIGN);
}
/* Load/store register (all forms) */
--
2.17.0
- [Qemu-devel] [PULL 01/21] hw/arm/iotkit.c: fix minor memory leak, (continued)
- [Qemu-devel] [PULL 01/21] hw/arm/iotkit.c: fix minor memory leak, Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 07/21] atomic.h: Work around gcc spurious "unused value" warning, Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 08/21] tcg: Introduce helpers for integer min/max, Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 06/21] make sure that we aren't overwriting mc->get_hotplug_handler by accident, Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 09/21] target/arm: Use new min/max expanders, Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 10/21] target/xtensa: Use new min/max expanders, Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 05/21] arm/boot: split load_dtb() from arm_load_kernel(), Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 12/21] tcg: Use GEN_ATOMIC_HELPER_FN for opposite endian atomic add, Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 11/21] tcg: Introduce atomic helpers for integer min/max, Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 04/21] platform-bus-device: use device plug callback instead of machine_done notifier, Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 15/21] target/arm: Fill in disas_ldst_atomic,
Peter Maydell <=
- [Qemu-devel] [PULL 13/21] target/riscv: Use new atomic min/max expanders, Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 17/21] target/arm: Enable ARM_FEATURE_V8_ATOMICS for user-only, Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 16/21] target/arm: Implement CAS and CASP, Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 18/21] target/arm: Implement vector shifted SCVF/UCVF for fp16, Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 14/21] target/arm: Introduce ARM_FEATURE_V8_ATOMICS and initial decode, Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 20/21] target/arm: Fix float16 to/from int16, Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 19/21] target/arm: Implement vector shifted FCVT for fp16, Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 21/21] target/arm: Clear SVE high bits for FMOV, Peter Maydell, 2018/05/10
- Re: [Qemu-devel] [PULL 00/21] target-arm queue, no-reply, 2018/05/10
- Re: [Qemu-devel] [PULL 00/21] target-arm queue, Peter Maydell, 2018/05/14