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Re: [Qemu-devel] [Qemu-arm] [PATCH v1 1/2] target-arm: Add the Cortex-R5
From: |
Philippe Mathieu-Daudé |
Subject: |
Re: [Qemu-devel] [Qemu-arm] [PATCH v1 1/2] target-arm: Add the Cortex-R5F |
Date: |
Thu, 10 May 2018 14:59:37 -0300 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 |
On 05/03/2018 08:56 AM, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <address@hidden>
>
> Add the Cortex-R5F with the optional FPU enabled.
>
> Signed-off-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Tested-by: Philippe Mathieu-Daudé <address@hidden>
> ---
> target/arm/cpu.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index d175c5e94f..7a7035c037 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -1341,6 +1341,14 @@ static void cortex_r5_initfn(Object *obj)
> define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
> }
>
> +static void cortex_r5f_initfn(Object *obj)
> +{
> + ARMCPU *cpu = ARM_CPU(obj);
> +
> + cortex_r5_initfn(obj);
> + set_feature(&cpu->env, ARM_FEATURE_VFP3);
> +}
> +
> static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
> { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 =
> 0,
> .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
> @@ -1801,6 +1809,7 @@ static const ARMCPUInfo arm_cpus[] = {
> { .name = "cortex-m33", .initfn = cortex_m33_initfn,
> .class_init = arm_v7m_class_init },
> { .name = "cortex-r5", .initfn = cortex_r5_initfn },
> + { .name = "cortex-r5f", .initfn = cortex_r5f_initfn },
> { .name = "cortex-a7", .initfn = cortex_a7_initfn },
> { .name = "cortex-a8", .initfn = cortex_a8_initfn },
> { .name = "cortex-a9", .initfn = cortex_a9_initfn },
>