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[Qemu-devel] [PATCH 4/9] target/riscv: Introduce cpu_riscv_get_fcsr
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 4/9] target/riscv: Introduce cpu_riscv_get_fcsr |
Date: |
Thu, 10 May 2018 20:52:35 -0700 |
Cc: Michael Clark <address@hidden>
Cc: Palmer Dabbelt <address@hidden>
Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/riscv/cpu.h | 1 +
target/riscv/fpu_helper.c | 6 ++++++
target/riscv/op_helper.c | 3 +--
3 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 34abc383e3..f2bc243b95 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -265,6 +265,7 @@ void QEMU_NORETURN do_raise_exception_err(CPURISCVState
*env,
uint32_t exception, uintptr_t pc);
target_ulong cpu_riscv_get_fflags(CPURISCVState *env);
+target_ulong cpu_riscv_get_fcsr(CPURISCVState *env);
void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong);
#define TB_FLAGS_MMU_MASK 3
diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
index abbadead5c..41c7352115 100644
--- a/target/riscv/fpu_helper.c
+++ b/target/riscv/fpu_helper.c
@@ -37,6 +37,12 @@ target_ulong cpu_riscv_get_fflags(CPURISCVState *env)
return hard;
}
+target_ulong cpu_riscv_get_fcsr(CPURISCVState *env)
+{
+ return (cpu_riscv_get_fflags(env) << FSR_AEXC_SHIFT)
+ | (env->frm << FSR_RD_SHIFT);
+}
+
void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong hard)
{
int soft = 0;
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 3abf52453c..fd2d8c0a9d 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -423,8 +423,7 @@ target_ulong csr_read_helper(CPURISCVState *env,
target_ulong csrno)
return env->frm;
case CSR_FCSR:
validate_mstatus_fs(env, GETPC());
- return (cpu_riscv_get_fflags(env) << FSR_AEXC_SHIFT)
- | (env->frm << FSR_RD_SHIFT);
+ return cpu_riscv_get_fcsr(env);
/* rdtime/rdtimeh is trapped and emulated by bbl in system mode */
#ifdef CONFIG_USER_ONLY
case CSR_TIME:
--
2.17.0
- [Qemu-devel] [PATCH 0/9] Honor CPU_DUMP_FPU, Richard Henderson, 2018/05/10
- [Qemu-devel] [PATCH 1/9] target/alpha: Honor CPU_DUMP_FPU, Richard Henderson, 2018/05/10
- [Qemu-devel] [PATCH 2/9] target/mips: Honor CPU_DUMP_FPU, Richard Henderson, 2018/05/10
- [Qemu-devel] [PATCH 3/9] target/ppc: Honor CPU_DUMP_FPU, Richard Henderson, 2018/05/10
- [Qemu-devel] [PATCH 4/9] target/riscv: Introduce cpu_riscv_get_fcsr,
Richard Henderson <=
- [Qemu-devel] [PATCH 5/9] target/riscv: Honor CPU_DUMP_FPU, Richard Henderson, 2018/05/10
- [Qemu-devel] [PATCH 6/9] target/s390x: Honor CPU_DUMP_FPU, Richard Henderson, 2018/05/10
- [Qemu-devel] [PATCH 9/9] target/xtensa: Honor CPU_DUMP_FPU, Richard Henderson, 2018/05/10