Re: [Qemu-devel] [PATCH 0/9] target/arm: Fixups for ARM_FEATURE_V8_FP16

[Alex Bennée]

Richard Henderson <address@hidden> writes:

> On 04/27/2018 10:22 AM, Alex Bennée wrote:
>>
>> Richard Henderson <address@hidden> writes:
>>
>>> When running the gcc testsuite with current aarch64-linux-user,
>>> the testsuite detects the presence of the fp16 extension and
>>> enables lots of extra tests for builtins.
>>>
>>> Quite a few of these new tests fail because we missed implementing
>>> some instructions.  We really should go back and verify that nothing
>>> else is missing from this (rather large) extension.
>>
>> So this set of instructions is generated from any ASL description that
>> contains "half":
>
> This still isn't all of them.  At least the insns from fmov_float_gen.html are
> missing.  The four insns could be handled with
>
> FMOV_H_general  A64_V sf:1 00 11110 11 100 11 o:1 000000 Rn:5 Rd:5
>
> Peter had pointed out that I didn't handle sf=1 in fmov during review.

It describes itself as:

   <docvars>
       <docvar key="convert-type" value="32-to-half" />
       <docvar key="instr-class" value="float" />
       <docvar key="isa" value="A64" />
       <docvar key="mnemonic" value="FMOV" />
   </docvars>

I found I had to make the --desc matching a lot more liberal to catch
stuff from the Aarch32 XML, so now:

22:11:47 address@hidden:~/l/q/risu.git] add-asl-support-v2(+1/-1) + 
./contrib/armasl2risu.py --only-desc "half" xml/ISA_v83A_A64_xml_00bet6/*.xml | 
grep FMOV
FMOV_32H_float2int A64_V 0001111011100110000000 Rn:5  Rd:5
FMOV_H32_float2int A64_V 0001111011100111000000 Rn:5  Rd:5
FMOV_asimdimm_H_h A64_V 0 Q:1 00111100000 a:1  b:1  c:1 111111 d:1  e:1  f:1  
g:1  h:1  Rd:5
FMOV_H64_float2int A64_V 1001111011100111000000 Rn:5  Rd:5
FMOV_64H_float2int A64_V 1001111011100110000000 Rn:5  Rd:5
FMOV_H_floatimm A64_V 00011110111 imm8:8 10000000 Rd:5
FMOV_H_floatdp1 A64_V 0001111011100000010000 Rn:5  Rd:5

Whereas I had:

22:11:58 address@hidden:~/l/q/risu.git] add-asl-support-v2(+1/-1) + grep FMOV 
all_v82_half.risu
FMOV_H_floatimm A64_V 00011110111 imm8:8 10000000 Rd:5
FMOV_H_floatdp1 A64_V 0001111011100000010000 Rn:5  Rd:5

I'll regenerate a set.

--
Alex Bennée