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[Qemu-devel] [PATCH v3 10/12] intel-iommu: simplify page walk logic
From: |
Peter Xu |
Subject: |
[Qemu-devel] [PATCH v3 10/12] intel-iommu: simplify page walk logic |
Date: |
Thu, 17 May 2018 16:59:25 +0800 |
Let's move the notify_unmap check into the new vtd_page_walk_one()
function so that we can greatly simplify the vtd_page_walk_level()
logic.
No functional change at all.
Signed-off-by: Peter Xu <address@hidden>
---
hw/i386/intel_iommu.c | 66 ++++++++++++++++++++-----------------------
hw/i386/trace-events | 1 -
2 files changed, 30 insertions(+), 37 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 5a5175a4ed..272e49ff66 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -779,6 +779,11 @@ static int vtd_page_walk_one(IOMMUTLBEntry *entry,
vtd_page_walk_info *info)
};
DMAMap *mapped = iova_tree_find(as->iova_tree, &target);
+ if (entry->perm == IOMMU_NONE && !info->notify_unmap) {
+ trace_vtd_page_walk_one_skip_unmap(entry->iova, entry->addr_mask);
+ return 0;
+ }
+
assert(hook_fn);
/* Update local IOVA mapped ranges */
@@ -894,45 +899,34 @@ static int vtd_page_walk_level(dma_addr_t addr, uint64_t
start,
*/
entry_valid = read_cur | write_cur;
- entry.target_as = &address_space_memory;
- entry.iova = iova & subpage_mask;
- entry.perm = IOMMU_ACCESS_FLAG(read_cur, write_cur);
- entry.addr_mask = ~subpage_mask;
-
- if (vtd_is_last_slpte(slpte, level)) {
- /* NOTE: this is only meaningful if entry_valid == true */
- entry.translated_addr = vtd_get_slpte_addr(slpte, info->aw);
- if (!entry_valid && !info->notify_unmap) {
- trace_vtd_page_walk_skip_perm(iova, iova_next);
- goto next;
- }
- ret = vtd_page_walk_one(&entry, info);
- if (ret < 0) {
- return ret;
- }
- } else {
- if (!entry_valid) {
- if (info->notify_unmap) {
- /*
- * The whole entry is invalid; unmap it all.
- * Translated address is meaningless, zero it.
- */
- entry.translated_addr = 0x0;
- ret = vtd_page_walk_one(&entry, info);
- if (ret < 0) {
- return ret;
- }
- } else {
- trace_vtd_page_walk_skip_perm(iova, iova_next);
- }
- goto next;
- }
+ if (!vtd_is_last_slpte(slpte, level) && entry_valid) {
+ /*
+ * This is a valid PDE (or even bigger than PDE). We need
+ * to walk one further level.
+ */
ret = vtd_page_walk_level(vtd_get_slpte_addr(slpte, info->aw),
iova, MIN(iova_next, end), level - 1,
read_cur, write_cur, info);
- if (ret < 0) {
- return ret;
- }
+ } else {
+ /*
+ * This means we are either:
+ *
+ * (1) the real page entry (either 4K page, or huge page)
+ * (2) the whole range is invalid
+ *
+ * In either case, we send an IOTLB notification down.
+ */
+ entry.target_as = &address_space_memory;
+ entry.iova = iova & subpage_mask;
+ entry.perm = IOMMU_ACCESS_FLAG(read_cur, write_cur);
+ entry.addr_mask = ~subpage_mask;
+ /* NOTE: this is only meaningful if entry_valid == true */
+ entry.translated_addr = vtd_get_slpte_addr(slpte, info->aw);
+ ret = vtd_page_walk_one(&entry, info);
+ }
+
+ if (ret < 0) {
+ return ret;
}
next:
diff --git a/hw/i386/trace-events b/hw/i386/trace-events
index d8194b80e3..e14d06ec83 100644
--- a/hw/i386/trace-events
+++ b/hw/i386/trace-events
@@ -43,7 +43,6 @@ vtd_page_walk_one(uint16_t domain, uint64_t iova, uint64_t
gpa, uint64_t mask, i
vtd_page_walk_one_skip_map(uint64_t iova, uint64_t mask, uint64_t translated)
"iova 0x%"PRIx64" mask 0x%"PRIx64" translated 0x%"PRIx64
vtd_page_walk_one_skip_unmap(uint64_t iova, uint64_t mask) "iova 0x%"PRIx64"
mask 0x%"PRIx64
vtd_page_walk_skip_read(uint64_t iova, uint64_t next) "Page walk skip iova
0x%"PRIx64" - 0x%"PRIx64" due to unable to read"
-vtd_page_walk_skip_perm(uint64_t iova, uint64_t next) "Page walk skip iova
0x%"PRIx64" - 0x%"PRIx64" due to perm empty"
vtd_page_walk_skip_reserve(uint64_t iova, uint64_t next) "Page walk skip iova
0x%"PRIx64" - 0x%"PRIx64" due to rsrv set"
vtd_switch_address_space(uint8_t bus, uint8_t slot, uint8_t fn, bool on)
"Device %02x:%02x.%x switching address space (iommu enabled=%d)"
vtd_as_unmap_whole(uint8_t bus, uint8_t slot, uint8_t fn, uint64_t iova,
uint64_t size) "Device %02x:%02x.%x start 0x%"PRIx64" size 0x%"PRIx64
--
2.17.0
- Re: [Qemu-devel] [PATCH v3 01/12] intel-iommu: send PSI always even if across PDEs, (continued)
- [Qemu-devel] [PATCH v3 02/12] intel-iommu: remove IntelIOMMUNotifierNode, Peter Xu, 2018/05/17
- [Qemu-devel] [PATCH v3 03/12] intel-iommu: add iommu lock, Peter Xu, 2018/05/17
- [Qemu-devel] [PATCH v3 04/12] intel-iommu: only do page walk for MAP notifiers, Peter Xu, 2018/05/17
- [Qemu-devel] [PATCH v3 05/12] intel-iommu: introduce vtd_page_walk_info, Peter Xu, 2018/05/17
- [Qemu-devel] [PATCH v3 06/12] intel-iommu: pass in address space when page walk, Peter Xu, 2018/05/17
- [Qemu-devel] [PATCH v3 07/12] intel-iommu: trace domain id during page walk, Peter Xu, 2018/05/17
- [Qemu-devel] [PATCH v3 08/12] util: implement simple iova tree, Peter Xu, 2018/05/17
- [Qemu-devel] [PATCH v3 09/12] intel-iommu: maintain per-device iova ranges, Peter Xu, 2018/05/17
- [Qemu-devel] [PATCH v3 10/12] intel-iommu: simplify page walk logic,
Peter Xu <=
- [Qemu-devel] [PATCH v3 11/12] intel-iommu: new vtd_sync_shadow_page_table_range, Peter Xu, 2018/05/17
- [Qemu-devel] [PATCH v3 12/12] intel-iommu: new sync_shadow_page_table, Peter Xu, 2018/05/17
- Re: [Qemu-devel] [PATCH v3 00/12] intel-iommu: nested vIOMMU, cleanups, bug fixes, Jintack Lim, 2018/05/17
- Re: [Qemu-devel] [PATCH v3 00/12] intel-iommu: nested vIOMMU, cleanups, bug fixes, Michael S. Tsirkin, 2018/05/17
- Re: [Qemu-devel] [PATCH v3 00/12] intel-iommu: nested vIOMMU, cleanups, bug fixes, Michael S. Tsirkin, 2018/05/17