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Re: [Qemu-devel] [PATCH v3 2/7] hw/riscv/sifive_e: Create a SiFive E SoC
From: |
Michael Clark |
Subject: |
Re: [Qemu-devel] [PATCH v3 2/7] hw/riscv/sifive_e: Create a SiFive E SoC object |
Date: |
Fri, 18 May 2018 14:12:02 +1200 |
On Tue, May 15, 2018 at 12:07 PM, Alistair Francis <address@hidden
> wrote:
> Signed-off-by: Alistair Francis <address@hidden>
>
Reviewed-by: Michael Clark <address@hidden>
> ---
> hw/riscv/sifive_e.c | 97 +++++++++++++++++++++++++++----------
> include/hw/riscv/sifive_e.h | 16 +++++-
> 2 files changed, 86 insertions(+), 27 deletions(-)
>
> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> index e4ecb7aa4b..384b456540 100644
> --- a/hw/riscv/sifive_e.c
> +++ b/hw/riscv/sifive_e.c
> @@ -102,18 +102,12 @@ static void riscv_sifive_e_init(MachineState
> *machine)
> SiFiveEState *s = g_new0(SiFiveEState, 1);
> MemoryRegion *sys_mem = get_system_memory();
> MemoryRegion *main_mem = g_new(MemoryRegion, 1);
> - MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
> - MemoryRegion *xip_mem = g_new(MemoryRegion, 1);
> int i;
>
> - /* Initialize SOC */
> - object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY);
> + /* Initialize SoC */
> + object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_E_SOC);
> object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
> &error_abort);
> - object_property_set_str(OBJECT(&s->soc), SIFIVE_E_CPU, "cpu-type",
> - &error_abort);
> - object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
> - &error_abort);
> object_property_set_bool(OBJECT(&s->soc), true, "realized",
> &error_abort);
>
> @@ -123,11 +117,57 @@ static void riscv_sifive_e_init(MachineState
> *machine)
> memory_region_add_subregion(sys_mem,
> memmap[SIFIVE_E_DTIM].base, main_mem);
>
> + /* Mask ROM reset vector */
> + uint32_t reset_vec[2] = {
> + 0x204002b7, /* 0x1000: lui t0,0x20400 */
> + 0x00028067, /* 0x1004: jr t0 */
> + };
> +
> + /* copy in the reset vector in little_endian byte order */
> + for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
> + reset_vec[i] = cpu_to_le32(reset_vec[i]);
> + }
> + rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
> + memmap[SIFIVE_E_MROM].base,
> &address_space_memory);
> +
> + if (machine->kernel_filename) {
> + load_kernel(machine->kernel_filename);
> + }
> +}
> +
> +static void riscv_sifive_e_soc_init(Object *obj)
> +{
> + const struct MemmapEntry *memmap = sifive_e_memmap;
> +
> + SiFiveESoCState *s = RISCV_E_SOC(obj);
> + MemoryRegion *sys_mem = get_system_memory();
> + MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
> +
> + object_initialize(&s->cpus, sizeof(s->cpus), TYPE_RISCV_HART_ARRAY);
> + object_property_add_child(obj, "cpus", OBJECT(&s->cpus),
> + &error_abort);
> + object_property_set_str(OBJECT(&s->cpus), SIFIVE_E_CPU, "cpu-type",
> + &error_abort);
> + object_property_set_int(OBJECT(&s->cpus), smp_cpus, "num-harts",
> + &error_abort);
> +
> /* Mask ROM */
> memory_region_init_rom(mask_rom, NULL, "riscv.sifive.e.mrom",
> memmap[SIFIVE_E_MROM].size, &error_fatal);
> memory_region_add_subregion(sys_mem,
> memmap[SIFIVE_E_MROM].base, mask_rom);
> +}
> +
> +static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
> +{
> + const struct MemmapEntry *memmap = sifive_e_memmap;
> +
> + SiFiveESoCState *s = RISCV_E_SOC(dev);
> + MemoryRegion *sys_mem = get_system_memory();
> + MemoryRegion *xip_mem = g_new(MemoryRegion, 1);
> +
> + object_property_set_bool(OBJECT(&s->cpus), true, "realized",
> + &error_abort);
>
> /* MMIO */
> s->plic = sifive_plic_create(memmap[SIFIVE_E_PLIC].base,
> @@ -171,23 +211,6 @@ static void riscv_sifive_e_init(MachineState
> *machine)
> memmap[SIFIVE_E_XIP].size, &error_fatal);
> memory_region_set_readonly(xip_mem, true);
> memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_XIP].base,
> xip_mem);
> -
> - /* Mask ROM reset vector */
> - uint32_t reset_vec[2] = {
> - 0x204002b7, /* 0x1000: lui t0,0x20400 */
> - 0x00028067, /* 0x1004: jr t0 */
> - };
> -
> - /* copy in the reset vector in little_endian byte order */
> - for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
> - reset_vec[i] = cpu_to_le32(reset_vec[i]);
> - }
> - rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
> - memmap[SIFIVE_E_MROM].base,
> &address_space_memory);
> -
> - if (machine->kernel_filename) {
> - load_kernel(machine->kernel_filename);
> - }
> }
>
> static void riscv_sifive_e_machine_init(MachineClass *mc)
> @@ -198,3 +221,27 @@ static void riscv_sifive_e_machine_init(MachineClass
> *mc)
> }
>
> DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init)
> +
> +static void riscv_sifive_e_soc_class_init(ObjectClass *oc, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(oc);
> +
> + dc->realize = riscv_sifive_e_soc_realize;
> + /* Reason: Uses serial_hds in realize function, thus can't be used
> twice */
> + dc->user_creatable = false;
> +}
> +
> +static const TypeInfo riscv_sifive_e_soc_type_info = {
> + .name = TYPE_RISCV_E_SOC,
> + .parent = TYPE_DEVICE,
> + .instance_size = sizeof(SiFiveESoCState),
> + .instance_init = riscv_sifive_e_soc_init,
> + .class_init = riscv_sifive_e_soc_class_init,
> +};
> +
> +static void riscv_sifive_e_soc_register_types(void)
> +{
> + type_register_static(&riscv_sifive_e_soc_type_info);
> +}
> +
> +type_init(riscv_sifive_e_soc_register_types)
> diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
> index 12ad6d2ebb..7b6d8aed96 100644
> --- a/include/hw/riscv/sifive_e.h
> +++ b/include/hw/riscv/sifive_e.h
> @@ -19,13 +19,25 @@
> #ifndef HW_SIFIVE_E_H
> #define HW_SIFIVE_E_H
>
> -typedef struct SiFiveEState {
> +#define TYPE_RISCV_E_SOC "riscv.sifive.e.soc"
> +#define RISCV_E_SOC(obj) \
> + OBJECT_CHECK(SiFiveESoCState, (obj), TYPE_RISCV_E_SOC)
> +
> +typedef struct SiFiveESoCState {
> /*< private >*/
> SysBusDevice parent_obj;
>
> /*< public >*/
> - RISCVHartArrayState soc;
> + RISCVHartArrayState cpus;
> DeviceState *plic;
> +} SiFiveESoCState;
> +
> +typedef struct SiFiveEState {
> + /*< private >*/
> + SysBusDevice parent_obj;
> +
> + /*< public >*/
> + SiFiveESoCState soc;
> } SiFiveEState;
>
> enum {
> --
> 2.17.0
>
>
- [Qemu-devel] [PATCH v3 0/7] RISC-V: SoCify SiFive boards and connect GEM, Alistair Francis, 2018/05/14
- [Qemu-devel] [PATCH v3 1/7] hw/riscv/sifive_u: Create a SiFive U SoC object, Alistair Francis, 2018/05/14
- [Qemu-devel] [PATCH v3 2/7] hw/riscv/sifive_e: Create a SiFive E SoC object, Alistair Francis, 2018/05/14
- Re: [Qemu-devel] [PATCH v3 2/7] hw/riscv/sifive_e: Create a SiFive E SoC object,
Michael Clark <=
- [Qemu-devel] [PATCH v3 3/7] hw/riscv/sifive_plic: Use gpios instead of irqs, Alistair Francis, 2018/05/14
- [Qemu-devel] [PATCH v3 4/7] hw/riscv/sifive_u: Set the soc device tree node as a simple-bus, Alistair Francis, 2018/05/14
- [Qemu-devel] [PATCH v3 5/7] hw/riscv/sifive_u: Set the interrupt controler number of interrupts, Alistair Francis, 2018/05/14
- [Qemu-devel] [PATCH v3 6/7] hw/riscv/sifive_u: Move the uart device tree node under /soc/, Alistair Francis, 2018/05/14
- [Qemu-devel] [PATCH v3 7/7] hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device, Alistair Francis, 2018/05/14