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Re: [Qemu-devel] [PATCH v1 27/30] elf: Add RISC-V PSABI ELF header defin
From: |
Michael Clark |
Subject: |
Re: [Qemu-devel] [PATCH v1 27/30] elf: Add RISC-V PSABI ELF header defines |
Date: |
Fri, 25 May 2018 19:17:54 +1200 |
On Wed, May 23, 2018 at 6:44 PM, Laurent Vivier <address@hidden> wrote:
> Le 23/05/2018 à 02:15, Michael Clark a écrit :
> > Refer to the RISC-V PSABI specification for details:
> >
> > - https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md
> >
> > Cc: Michael Tokarev <address@hidden>
> > Cc: Laurent Vivier <address@hidden>
> > Cc: Richard Henderson <address@hidden>
> > Cc: Alistair Francis <address@hidden>
> > Signed-off-by: Michael Clark <address@hidden>
> > ---
> > include/elf.h | 8 ++++++++
> > 1 file changed, 8 insertions(+)
> >
> > diff --git a/include/elf.h b/include/elf.h
> > index 934dbbd6b3ae..d363ba85a688 100644
> > --- a/include/elf.h
> > +++ b/include/elf.h
> > @@ -1285,6 +1285,14 @@ typedef struct {
> > #define R_IA64_DTPREL64LSB 0xb7 /* @dtprel(sym + add), data8 LSB */
> > #define R_IA64_LTOFF_DTPREL22 0xba /* @ltoff(@dtprel(s+a)),
> imm22 */
> >
> > +/* RISC-V specific definitions. */
> > +#define EF_RISCV_RVC 0x0001
> > +#define EF_RISCV_FLOAT_ABI_SINGLE 0x0002
> > +#define EF_RISCV_FLOAT_ABI_DOUBLE 0x0004
> > +#define EF_RISCV_FLOAT_ABI_QUAD (0x0006
> ^
> Typo here -------------------------|
>
Thanks! My mistake.
The original patch had only EF_RISCV_RVE, which is the define we need for a
subsequent patch, however I decided to add the remaining flags from the
spec and indeed there was a paren in the spec.
I'll respin this as a separate patch.
- Re: [Qemu-devel] [PATCH v1 20/30] RISC-V: Add misa to DisasContext, (continued)
- [Qemu-devel] [PATCH v1 21/30] RISC-V: Add misa.MAFD checks to translate, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 22/30] RISC-V: Add misa runtime write support, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 23/30] RISC-V: Fix CLINT timecmp low 32-bit writes, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 24/30] RISC-V: Fix PLIC pending bitfield reads, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 25/30] RISC-V: Enable second UART on sifive_e and sifive_u, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 26/30] RISC-V: Remove unnecessary disassembler constraints, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 27/30] elf: Add RISC-V PSABI ELF header defines, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 28/30] RISC-V: linux-user support for RVE ABI, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 29/30] RISC-V: Don't add NULL bootargs to device-tree, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 30/30] RISC-V: Support separate firmware and kernel payload, Michael Clark, 2018/05/22