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[Qemu-devel] [RISU PATCH v3 13/22] risu: move optional args to each arch
From: |
Alex Bennée |
Subject: |
[Qemu-devel] [RISU PATCH v3 13/22] risu: move optional args to each architecture |
Date: |
Wed, 13 Jun 2018 13:55:52 +0100 |
The key variables here are: *arch_long_opts and *arch_extra_help. If
they are not NULL then we concatenate the extra options to appropriate
structure to enable the support. Adding architecture short options is
not supported.
This also includes moving the ARM specific test_fp_exc/test-fp-exc
into ARM specific code.
Signed-off-by: Alex Bennée <address@hidden>
---
v2
- better concatenation of default and extra opts
---
risu.c | 29 +++++++++++++++++++++++++----
risu.h | 6 ++++--
risu_reginfo_aarch64.c | 3 +++
risu_reginfo_arm.c | 11 +++++++++++
risu_reginfo_m68k.c | 3 +++
risu_reginfo_ppc64.c | 3 +++
6 files changed, 49 insertions(+), 6 deletions(-)
diff --git a/risu.c b/risu.c
index c684c90..18de351 100644
--- a/risu.c
+++ b/risu.c
@@ -46,8 +46,7 @@ gzFile gz_trace_file;
sigjmp_buf jmpbuf;
-/* Should we test for FP exception status bits? */
-int test_fp_exc;
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
/* Master functions */
@@ -283,6 +282,9 @@ void usage(void)
fprintf(stderr,
" -p, --port=PORT Specify the port to connect to/listen on "
"(default 9191)\n");
+ if (arch_extra_help) {
+ fprintf(stderr, "%s", arch_extra_help);
+ }
}
struct option * setup_options(char **short_opts)
@@ -293,12 +295,31 @@ struct option * setup_options(char **short_opts)
{"host", required_argument, 0, 'h'},
{"port", required_argument, 0, 'p'},
{"trace", required_argument, 0, 't'},
- {"test-fp-exc", no_argument, &test_fp_exc, 1},
{0, 0, 0, 0}
};
+ struct option *lopts = &default_longopts[0];
*short_opts = "h:p:t:";
- return default_longopts;
+
+ if (arch_long_opts) {
+ const size_t osize = sizeof(struct option);
+ const int default_count = ARRAY_SIZE(default_longopts);
+ struct option *dptr;
+ int extra_count = 0;
+
+ /* count additional opts */
+ dptr = arch_long_opts;
+ do {} while (dptr[extra_count++].name);
+
+ lopts = calloc(default_count + extra_count, osize);
+
+ /* Copy default opts + extra opts */
+ memcpy(lopts, default_longopts, default_count * osize);
+ dptr = &lopts[default_count - 1];
+ memcpy(dptr, arch_long_opts, extra_count * osize);
+ }
+
+ return lopts;
}
int main(int argc, char **argv)
diff --git a/risu.h b/risu.h
index 1c8ecee..89811f4 100644
--- a/risu.h
+++ b/risu.h
@@ -17,6 +17,10 @@
#include <ucontext.h>
#include <stdio.h>
+/* Extra option processing for architectures */
+extern void *arch_long_opts;
+extern char *arch_extra_help;
+
/* GCC computed include to pull in the correct risu_reginfo_*.h for
* the architecture.
*/
@@ -36,8 +40,6 @@ void send_response_byte(int sock, int resp);
extern uintptr_t image_start_address;
extern void *memblock;
-extern int test_fp_exc;
-
/* Ops code under test can request from risu: */
#define OP_COMPARE 0
#define OP_TESTEND 1
diff --git a/risu_reginfo_aarch64.c b/risu_reginfo_aarch64.c
index 3bb4339..ab12270 100644
--- a/risu_reginfo_aarch64.c
+++ b/risu_reginfo_aarch64.c
@@ -18,6 +18,9 @@
#include "risu.h"
#include "risu_reginfo_aarch64.h"
+void *arch_long_opts;
+char *arch_extra_help;
+
/* reginfo_init: initialize with a ucontext */
void reginfo_init(struct reginfo *ri, ucontext_t *uc)
{
diff --git a/risu_reginfo_arm.c b/risu_reginfo_arm.c
index 6b9ee7b..5acad02 100644
--- a/risu_reginfo_arm.c
+++ b/risu_reginfo_arm.c
@@ -13,12 +13,23 @@
#include <stdio.h>
#include <ucontext.h>
#include <string.h>
+#include <getopt.h>
#include "risu.h"
#include "risu_reginfo_arm.h"
extern int insnsize(ucontext_t *uc);
+/* Should we test for FP exception status bits? */
+static int test_fp_exc;
+static struct option extra_opts[] = {
+ {"test-fp-exc", no_argument, &test_fp_exc, 1},
+ {0, 0, 0, 0}
+};
+
+void *arch_long_opts = &extra_opts[0];
+char *arch_extra_help = " --test-fp-exc Check FP exception bits when
comparing\n";
+
static void reginfo_init_vfp(struct reginfo *ri, ucontext_t *uc)
{
/* Read VFP registers. These live in uc->uc_regspace, which is
diff --git a/risu_reginfo_m68k.c b/risu_reginfo_m68k.c
index 4ff0aa8..d429502 100644
--- a/risu_reginfo_m68k.c
+++ b/risu_reginfo_m68k.c
@@ -14,6 +14,9 @@
#include "risu.h"
#include "risu_reginfo_m68k.h"
+void *arch_long_opts;
+char *arch_extra_help;
+
/* reginfo_init: initialize with a ucontext */
void reginfo_init(struct reginfo *ri, ucontext_t *uc)
{
diff --git a/risu_reginfo_ppc64.c b/risu_reginfo_ppc64.c
index 5f33648..395111c 100644
--- a/risu_reginfo_ppc64.c
+++ b/risu_reginfo_ppc64.c
@@ -22,6 +22,9 @@
#define XER 37
#define CCR 38
+void *arch_long_opts;
+char *arch_extra_help;
+
/* reginfo_init: initialize with a ucontext */
void reginfo_init(struct reginfo *ri, ucontext_t *uc)
{
--
2.17.1
- [Qemu-devel] [RISU PATCH v3 16/22] risu_reginfo_aarch64: unionify VFP regs, (continued)
- [Qemu-devel] [RISU PATCH v3 16/22] risu_reginfo_aarch64: unionify VFP regs, Alex Bennée, 2018/06/13
- [Qemu-devel] [RISU PATCH v3 18/22] risu_reginfo_aarch64: left justify regnums and drop masks, Alex Bennée, 2018/06/13
- [Qemu-devel] [RISU PATCH v3 21/22] risu_reginfo_aarch64: limit SVE_VQ_MAX to current architecture, Alex Bennée, 2018/06/13
- [Qemu-devel] [RISU PATCH v3 19/22] risu_reginfo_aarch64: add support for copying SVE register state, Alex Bennée, 2018/06/13
- [Qemu-devel] [RISU PATCH v3 14/22] risu: add process_arch_opt, Alex Bennée, 2018/06/13
- [Qemu-devel] [RISU PATCH v3 22/22] risu_reginfo_aarch64: handle variable VQ, Alex Bennée, 2018/06/13
- [Qemu-devel] [RISU PATCH v3 20/22] risu_reginfo_aarch64: add SVE support to reginfo_dump_mismatch, Alex Bennée, 2018/06/13
- [Qemu-devel] [RISU PATCH v3 12/22] contrib/generate_all.sh: allow passing of arguments to risugen, Alex Bennée, 2018/06/13
- [Qemu-devel] [RISU PATCH v3 13/22] risu: move optional args to each architecture,
Alex Bennée <=