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Re: [Qemu-devel] [PATCH v4] aspeed_scu: Implement RNG register


From: Peter Maydell
Subject: Re: [Qemu-devel] [PATCH v4] aspeed_scu: Implement RNG register
Date: Fri, 15 Jun 2018 11:35:25 +0100

On 13 June 2018 at 12:48, Joel Stanley <address@hidden> wrote:
> The ASPEED SoCs contain a single register that returns random data when
> read. This models that register so that guests can use it.
>
> The random number data register has a corresponding control register,
> however it returns data regardless of the state of the enabled bit, so
> the model follows this behaviour.
>
> When the qcrypto call fails we exit as the guest uses the random number
> device to feed it's entropy pool, which is used for cryptographic
> purposes.
>
> Reviewed-by: C├ędric Le Goater <address@hidden>
> Signed-off-by: Joel Stanley <address@hidden>
> ---



Applied to target-arm.next, thanks.

-- PMM



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