[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 28/43] target/arm: Implement SVE Select Vectors Group
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 28/43] target/arm: Implement SVE Select Vectors Group |
Date: |
Fri, 15 Jun 2018 15:25:06 +0100 |
From: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/helper-sve.h | 9 +++++++
target/arm/sve_helper.c | 55 ++++++++++++++++++++++++++++++++++++++
target/arm/translate-sve.c | 2 ++
target/arm/sve.decode | 6 +++++
4 files changed, 72 insertions(+)
diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
index c3f8a2b5021..0f57f64895b 100644
--- a/target/arm/helper-sve.h
+++ b/target/arm/helper-sve.h
@@ -195,6 +195,15 @@ DEF_HELPER_FLAGS_5(sve_lsl_zpzz_s, TCG_CALL_NO_RWG,
DEF_HELPER_FLAGS_5(sve_lsl_zpzz_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(sve_sel_zpzz_b, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(sve_sel_zpzz_h, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(sve_sel_zpzz_s, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(sve_sel_zpzz_d, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+
DEF_HELPER_FLAGS_5(sve_asr_zpzw_b, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_asr_zpzw_h, TCG_CALL_NO_RWG,
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index 8da7baad764..f55fdc7dbef 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -2146,3 +2146,58 @@ void HELPER(sve_splice)(void *vd, void *vn, void *vm,
void *vg, uint32_t desc)
}
swap_memmove(vd + len, vm, opr_sz * 8 - len);
}
+
+void HELPER(sve_sel_zpzz_b)(void *vd, void *vn, void *vm,
+ void *vg, uint32_t desc)
+{
+ intptr_t i, opr_sz = simd_oprsz(desc) / 8;
+ uint64_t *d = vd, *n = vn, *m = vm;
+ uint8_t *pg = vg;
+
+ for (i = 0; i < opr_sz; i += 1) {
+ uint64_t nn = n[i], mm = m[i];
+ uint64_t pp = expand_pred_b(pg[H1(i)]);
+ d[i] = (nn & pp) | (mm & ~pp);
+ }
+}
+
+void HELPER(sve_sel_zpzz_h)(void *vd, void *vn, void *vm,
+ void *vg, uint32_t desc)
+{
+ intptr_t i, opr_sz = simd_oprsz(desc) / 8;
+ uint64_t *d = vd, *n = vn, *m = vm;
+ uint8_t *pg = vg;
+
+ for (i = 0; i < opr_sz; i += 1) {
+ uint64_t nn = n[i], mm = m[i];
+ uint64_t pp = expand_pred_h(pg[H1(i)]);
+ d[i] = (nn & pp) | (mm & ~pp);
+ }
+}
+
+void HELPER(sve_sel_zpzz_s)(void *vd, void *vn, void *vm,
+ void *vg, uint32_t desc)
+{
+ intptr_t i, opr_sz = simd_oprsz(desc) / 8;
+ uint64_t *d = vd, *n = vn, *m = vm;
+ uint8_t *pg = vg;
+
+ for (i = 0; i < opr_sz; i += 1) {
+ uint64_t nn = n[i], mm = m[i];
+ uint64_t pp = expand_pred_s(pg[H1(i)]);
+ d[i] = (nn & pp) | (mm & ~pp);
+ }
+}
+
+void HELPER(sve_sel_zpzz_d)(void *vd, void *vn, void *vm,
+ void *vg, uint32_t desc)
+{
+ intptr_t i, opr_sz = simd_oprsz(desc) / 8;
+ uint64_t *d = vd, *n = vn, *m = vm;
+ uint8_t *pg = vg;
+
+ for (i = 0; i < opr_sz; i += 1) {
+ uint64_t nn = n[i], mm = m[i];
+ d[i] = (pg[H1(i)] & 1 ? nn : mm);
+ }
+}
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 1517d82468b..0de9118fdfb 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -373,6 +373,8 @@ static bool trans_UDIV_zpzz(DisasContext *s, arg_rprr_esz
*a, uint32_t insn)
return do_zpzz_ool(s, a, fns[a->esz]);
}
+DO_ZPZZ(SEL, sel)
+
#undef DO_ZPZZ
/*
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index a9fa6312522..91522d8e137 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -98,6 +98,7 @@
&rprr_esz rn=%reg_movprfx
@rdm_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 \
&rprr_esz rm=%reg_movprfx
address@hidden ........ esz:2 . rm:5 .. pg:4 rn:5 rd:5 &rprr_esz
# Three register operand, with governing predicate, vector element size
@rda_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 rd:5 \
@@ -466,6 +467,11 @@ RBIT 00000101 .. 1001 11 100 ... ..... .....
@rd_pg_rn
# SVE vector splice (predicated)
SPLICE 00000101 .. 101 100 100 ... ..... ..... @rdn_pg_rm
+### SVE Select Vectors Group
+
+# SVE select vector elements (predicated)
+SEL_zpzz 00000101 .. 1 ..... 11 .... ..... ..... @rd_pg4_rn_rm
+
### SVE Predicate Logical Operations Group
# SVE predicate logical operations
--
2.17.1
- [Qemu-devel] [PULL 03/43] hw/sh/sh7750: Convert away from old_mmio, (continued)
- [Qemu-devel] [PULL 03/43] hw/sh/sh7750: Convert away from old_mmio, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 20/43] target/arm: Implement SVE Permute - Unpredicated Group, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 25/43] target/arm: Implement SVE copy to vector (predicated), Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 24/43] target/arm: Implement SVE conditionally broadcast/extract element, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 02/43] hw/arm/mps2-tz: Put ethernet controller behind PPC, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 26/43] target/arm: Implement SVE reverse within elements, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 30/43] target/arm: Implement SVE Integer Compare - Immediate Group, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 33/43] target/arm: Implement SVE Integer Compare - Scalars Group, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 34/43] target/arm: Implement FDUP/DUP, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 31/43] target/arm: Implement SVE Partition Break Group, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 28/43] target/arm: Implement SVE Select Vectors Group,
Peter Maydell <=
- [Qemu-devel] [PULL 41/43] iommu: Add IOMMU index argument to translate method, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 42/43] exec.c: Handle IOMMUs in address_space_translate_for_iotlb(), Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 22/43] target/arm: Implement SVE Permute - Interleaving Group, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 27/43] target/arm: Implement SVE vector splice (predicated), Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 35/43] target/arm: Implement SVE Integer Wide Immediate - Unpredicated Group, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 29/43] target/arm: Implement SVE Integer Compare - Vectors Group, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 37/43] aspeed_scu: Implement RNG register, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 38/43] m25p80: add support for two bytes WRSR for Macronix chips, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 36/43] target/arm: Implement SVE Floating Point Arithmetic - Unpredicated Group, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 39/43] iommu: Add IOMMU index concept to IOMMU API, Peter Maydell, 2018/06/15