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[Qemu-devel] [PULL 02/28] ppc/spapr_caps: Don't disable cap_cfpc on POWE
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 02/28] ppc/spapr_caps: Don't disable cap_cfpc on POWER8 by default |
Date: |
Mon, 18 Jun 2018 13:52:58 +1000 |
From: Suraj Jitindar Singh <address@hidden>
In default_caps_with_cpu() we set spapr_cap_cfpc to broken for POWER8
processors and before.
Since we no longer require private l1d cache on POWER8 for this cap to
be set to workaround change this to default to broken for POWER7
processors and before.
Signed-off-by: Suraj Jitindar Singh <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
hw/ppc/spapr_caps.c | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c
index 531e145114..00e43a9ba7 100644
--- a/hw/ppc/spapr_caps.c
+++ b/hw/ppc/spapr_caps.c
@@ -335,14 +335,10 @@ static sPAPRCapabilities
default_caps_with_cpu(sPAPRMachineState *spapr,
caps = smc->default_caps;
- if (!ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00,
- 0, spapr->max_compat_pvr)) {
- caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN;
- }
-
if (!ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07,
0, spapr->max_compat_pvr)) {
caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF;
+ caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN;
}
if (!ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06_PLUS,
--
2.17.1
- [Qemu-devel] [PULL 00/28] ppc-for-3.0 queue 20180618, David Gibson, 2018/06/17
- [Qemu-devel] [PULL 03/28] target/ppc: drop empty #if/#endif block, David Gibson, 2018/06/17
- [Qemu-devel] [PULL 02/28] ppc/spapr_caps: Don't disable cap_cfpc on POWER8 by default,
David Gibson <=
- [Qemu-devel] [PULL 04/28] spapr: fix leak in h_client_architecture_support(), David Gibson, 2018/06/17
- [Qemu-devel] [PULL 01/28] target/ppc: Don't require private l1d cache on POWER8 for cap_ppc_safe_cache, David Gibson, 2018/06/17
- [Qemu-devel] [PULL 08/28] mac_newworld: wire up programmer switch to NMI handler, David Gibson, 2018/06/17
- [Qemu-devel] [PULL 09/28] adb: fix read reg 3 byte ordering, David Gibson, 2018/06/17
- [Qemu-devel] [PULL 13/28] mos6522: only clear the shift register interrupt upon write, David Gibson, 2018/06/17
- [Qemu-devel] [PULL 05/28] ppc: introduce Core99MachinesState for the mac99 machine, David Gibson, 2018/06/17
- [Qemu-devel] [PULL 06/28] mac_newworld: add via machine option to control mac99 VIA/ADB configuration, David Gibson, 2018/06/17
- [Qemu-devel] [PULL 10/28] adb: add property to disable direct reg 3 writes, David Gibson, 2018/06/17
- [Qemu-devel] [PULL 07/28] mac_newworld: add gpios to macio devices with PMU enabled, David Gibson, 2018/06/17
- [Qemu-devel] [PULL 16/28] sm501: Do not clear read only bits when writing registers, David Gibson, 2018/06/17