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[Qemu-devel] [PULL 20/28] pnv: Clean up cpu realize path
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 20/28] pnv: Clean up cpu realize path |
Date: |
Mon, 18 Jun 2018 13:53:16 +1000 |
pnv_cpu_init() is only called from the the pnv cpu core realize path, and
really only can be called from there. So fold it into its caller, which
we also rename for brevity.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
---
hw/ppc/pnv_core.c | 56 ++++++++++++++++++-----------------------------
1 file changed, 21 insertions(+), 35 deletions(-)
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index 1e40f01e98..f4c41d89d6 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -54,28 +54,6 @@ static void pnv_cpu_reset(void *opaque)
env->msr |= MSR_HVB; /* Hypervisor mode */
}
-static void pnv_cpu_init(PowerPCCPU *cpu, Error **errp)
-{
- CPUPPCState *env = &cpu->env;
- int core_pir;
- int thread_index = 0; /* TODO: TCG supports only one thread */
- ppc_spr_t *pir = &env->spr_cb[SPR_PIR];
-
- core_pir = object_property_get_uint(OBJECT(cpu), "core-pir", &error_abort);
-
- /*
- * The PIR of a thread is the core PIR + the thread index. We will
- * need to find a way to get the thread index when TCG supports
- * more than 1. We could use the object name ?
- */
- pir->default_value = core_pir + thread_index;
-
- /* Set time-base frequency to 512 MHz */
- cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ);
-
- qemu_register_reset(pnv_cpu_reset, cpu);
-}
-
/*
* These values are read by the PowerNV HW monitors under Linux
*/
@@ -121,29 +99,39 @@ static const MemoryRegionOps pnv_core_xscom_ops = {
.endianness = DEVICE_BIG_ENDIAN,
};
-static void pnv_core_realize_child(Object *child, XICSFabric *xi, Error **errp)
+static void pnv_realize_vcpu(PowerPCCPU *cpu, XICSFabric *xi, Error **errp)
{
+ CPUPPCState *env = &cpu->env;
+ int core_pir;
+ int thread_index = 0; /* TODO: TCG supports only one thread */
+ ppc_spr_t *pir = &env->spr_cb[SPR_PIR];
Error *local_err = NULL;
- CPUState *cs = CPU(child);
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- object_property_set_bool(child, true, "realized", &local_err);
+ object_property_set_bool(OBJECT(cpu), true, "realized", &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
}
- cpu->intc = icp_create(child, TYPE_PNV_ICP, xi, &local_err);
+ cpu->intc = icp_create(OBJECT(cpu), TYPE_PNV_ICP, xi, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
}
- pnv_cpu_init(cpu, &local_err);
- if (local_err) {
- error_propagate(errp, local_err);
- return;
- }
+ core_pir = object_property_get_uint(OBJECT(cpu), "core-pir", &error_abort);
+
+ /*
+ * The PIR of a thread is the core PIR + the thread index. We will
+ * need to find a way to get the thread index when TCG supports
+ * more than 1. We could use the object name ?
+ */
+ pir->default_value = core_pir + thread_index;
+
+ /* Set time-base frequency to 512 MHz */
+ cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ);
+
+ qemu_register_reset(pnv_cpu_reset, cpu);
}
static void pnv_core_realize(DeviceState *dev, Error **errp)
@@ -178,9 +166,7 @@ static void pnv_core_realize(DeviceState *dev, Error **errp)
}
for (j = 0; j < cc->nr_threads; j++) {
- obj = OBJECT(pc->threads[j]);
-
- pnv_core_realize_child(obj, XICS_FABRIC(xi), &local_err);
+ pnv_realize_vcpu(pc->threads[j], XICS_FABRIC(xi), &local_err);
if (local_err) {
goto err;
}
--
2.17.1
- [Qemu-devel] [PULL 27/28] target/ppc, spapr: Move VPA information to machine_data, (continued)
- [Qemu-devel] [PULL 27/28] target/ppc, spapr: Move VPA information to machine_data, David Gibson, 2018/06/17
- [Qemu-devel] [PULL 11/28] mac_newworld: add PMU device, David Gibson, 2018/06/17
- [Qemu-devel] [PULL 23/28] spapr_cpu_core: fix potential leak in spapr_cpu_core_realize(), David Gibson, 2018/06/17
- [Qemu-devel] [PULL 14/28] mos6522: remove additional interrupt flag filter from mos6522_update_irq(), David Gibson, 2018/06/17
- [Qemu-devel] [PULL 22/28] spapr_cpu_core: convert last snprintf() to g_strdup_printf(), David Gibson, 2018/06/17
- [Qemu-devel] [PULL 12/28] xics_kvm: fix a build break, David Gibson, 2018/06/17
- [Qemu-devel] [PULL 24/28] spapr_cpu_core: add missing rollback on realization path, David Gibson, 2018/06/17
- [Qemu-devel] [PULL 21/28] pnv: Add cpu unrealize path, David Gibson, 2018/06/17
- [Qemu-devel] [PULL 26/28] ppc/pnv: introduce a pnv_chip_core_realize() routine, David Gibson, 2018/06/17
- [Qemu-devel] [PULL 17/28] spapr: Clean up cpu realize/unrealize paths, David Gibson, 2018/06/17
- [Qemu-devel] [PULL 20/28] pnv: Clean up cpu realize path,
David Gibson <=
- [Qemu-devel] [PULL 19/28] pnv_core: Allocate cpu thread objects individually, David Gibson, 2018/06/17
- [Qemu-devel] [PULL 28/28] spapr: fix xics_system_init() error path, David Gibson, 2018/06/17
- [Qemu-devel] [PULL 25/28] spapr_cpu_core: introduce spapr_create_vcpu(), David Gibson, 2018/06/17
- Re: [Qemu-devel] [PULL 00/28] ppc-for-3.0 queue 20180618, Peter Maydell, 2018/06/19