[Qemu-devel] [PATCH v2] docs: add guidance on configuring CPU models for x86

[Daniel P . Berrangé]

With the recent set of CPU hardware vulnerabilities on x86, it is
increasingly difficult to understand which CPU configurations are
good to use and what flaws they might be vulnerable to.

This doc attempts to help management applications and administrators in
picking sensible CPU configuration on x86 hosts. It outlines which of
the named CPU models are good choices, and describes which extra CPU
flags should be enabled to allow the guest to mitigate hardware flaws.

Signed-off-by: Daniel P. Berrangé <address@hidden>
---

Changed in v2:

  - Use texinfo so it can be pulled into main qemu-doc.texi
  - Build as a standalone  qemu-cpu-models(7) man page too

 MAINTAINERS               |   1 +
 Makefile                  |   7 +-
 docs/qemu-cpu-models.texi | 465 ++++++++++++++++++++++++++++++++++++++
 qemu-doc.texi             |   5 +
 4 files changed, 477 insertions(+), 1 deletion(-)
 create mode 100644 docs/qemu-cpu-models.texi

diff --git a/MAINTAINERS b/MAINTAINERS
index 8a94517e9e..ac1357cafa 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -285,6 +285,7 @@ S: Maintained
 F: target/i386/
 F: hw/i386/
 F: disas/i386.c
+F: docs/qemu-cpu-models.texi
 T: git git://github.com/ehabkost/qemu.git x86-next
 
 Xtensa
diff --git a/Makefile b/Makefile
index e46f2b625a..b232c8b0cb 100644
--- a/Makefile
+++ b/Makefile
@@ -359,6 +359,7 @@ DOCS=qemu-doc.html qemu-doc.txt qemu.1 qemu-img.1 
qemu-nbd.8 qemu-ga.8
 DOCS+=docs/interop/qemu-qmp-ref.html docs/interop/qemu-qmp-ref.txt 
docs/interop/qemu-qmp-ref.7
 DOCS+=docs/interop/qemu-ga-ref.html docs/interop/qemu-ga-ref.txt 
docs/interop/qemu-ga-ref.7
 DOCS+=docs/qemu-block-drivers.7
+DOCS+=docs/qemu-cpu-models.7
 ifdef CONFIG_VIRTFS
 DOCS+=fsdev/virtfs-proxy-helper.1
 endif
@@ -772,6 +773,7 @@ distclean: clean
        rm -f docs/interop/qemu-qmp-ref.pdf docs/interop/qemu-ga-ref.pdf
        rm -f docs/interop/qemu-qmp-ref.html docs/interop/qemu-ga-ref.html
        rm -f docs/qemu-block-drivers.7
+       rm -f docs/qemu-cpu-models.7
        for d in $(TARGET_LIST); do \
        rm -rf $$d || exit 1 ; \
         done
@@ -817,6 +819,7 @@ ifdef CONFIG_POSIX
        $(INSTALL_DIR) "$(DESTDIR)$(mandir)/man7"
        $(INSTALL_DATA) docs/interop/qemu-qmp-ref.7 "$(DESTDIR)$(mandir)/man7"
        $(INSTALL_DATA) docs/qemu-block-drivers.7 "$(DESTDIR)$(mandir)/man7"
+       $(INSTALL_DATA) docs/qemu-cpu-models.7 "$(DESTDIR)$(mandir)/man7"
 ifneq ($(TOOLS),)
        $(INSTALL_DATA) qemu-img.1 "$(DESTDIR)$(mandir)/man1"
        $(INSTALL_DIR) "$(DESTDIR)$(mandir)/man8"
@@ -959,6 +962,7 @@ fsdev/virtfs-proxy-helper.1: fsdev/virtfs-proxy-helper.texi
 qemu-nbd.8: qemu-nbd.texi qemu-option-trace.texi
 qemu-ga.8: qemu-ga.texi
 docs/qemu-block-drivers.7: docs/qemu-block-drivers.texi
+docs/qemu-cpu-models.7: docs/qemu-cpu-models.texi
 
 html: qemu-doc.html docs/interop/qemu-qmp-ref.html 
docs/interop/qemu-ga-ref.html
 info: qemu-doc.info docs/interop/qemu-qmp-ref.info 
docs/interop/qemu-ga-ref.info
@@ -968,7 +972,8 @@ txt: qemu-doc.txt docs/interop/qemu-qmp-ref.txt 
docs/interop/qemu-ga-ref.txt
 qemu-doc.html qemu-doc.info qemu-doc.pdf qemu-doc.txt: \
        qemu-img.texi qemu-nbd.texi qemu-options.texi qemu-option-trace.texi \
        qemu-monitor.texi qemu-img-cmds.texi qemu-ga.texi \
-       qemu-monitor-info.texi docs/qemu-block-drivers.texi
+       qemu-monitor-info.texi docs/qemu-block-drivers.texi \
+       docs/qemu-cpu-models.texi
 
 docs/interop/qemu-ga-ref.dvi docs/interop/qemu-ga-ref.html \
     docs/interop/qemu-ga-ref.info docs/interop/qemu-ga-ref.pdf \
diff --git a/docs/qemu-cpu-models.texi b/docs/qemu-cpu-models.texi
new file mode 100644
index 0000000000..889835ae24
--- /dev/null
+++ b/docs/qemu-cpu-models.texi
@@ -0,0 +1,465 @@
address@hidden man begin SYNOPSIS
+QEMU / KVM CPU model configuration
address@hidden man end
+
address@hidden man begin DESCRIPTION
+
+QEMU / KVM virtualization supports two ways to configure CPU models
+
address@hidden @option
+
address@hidden Host passthrough
+
+This passes the host CPU model features, model, stepping, exactly to the
+guest. Note that KVM may filter out some host CPU model features if they
+cannot be supported with virtualization. Live migration is unsafe when
+this mode is used as libvirt / QEMU cannot guarantee a stable CPU is
+exposed to the guest across hosts. This is the recommended CPU to use,
+provided live migration is not required.
+
address@hidden Named model
+
+QEMU comes with a number of predefined named CPU models, that typically
+refer to specific generations of hardware released by Intel and AMD.
+These allow the guest VMs to have a degree of isolation from the host CPU,
+allowing greater flexibility in live migrating between hosts with differing
+hardware.
address@hidden table
+
+In both cases, it is possible to optionally add or remove individual CPU
+features, to alter what is presented to the guest by default.
+
+Libvirt supports a third way to configure CPU models known as "Host model".
+This uses the QEMU "Named model" feature, automatically picking a CPU model
+that is similar the host CPU, and then adding extra features to approximate
+the host model as closely as possible. This does not guarantee the CPU family,
+stepping, etc will precisely match the host CPU, as they would with "Host
+passthrough", but gives much of the benefit of passthrough, while making
+live migration safe.
+
address@hidden recommendations_cpu_models_x86
address@hidden Recommendations for KVM CPU model configuration on x86 hosts
+
+The information that follows provides recommendations for configuring
+CPU models on x86 hosts. The goals are to maximise performance, while
+protecting guest OS against various CPU hardware flaws, and optionally
+enabling live migration between hosts with hetergeneous CPU models.
+
address@hidden preferred_cpu_models_intel_x86
address@hidden Preferred CPU models for Intel x86 hosts
+
+The following CPU models are preferred for use on Intel hosts. Administrators /
+applications are recommended to use the CPU model that matches the generation
+of the host CPUs in use. In a deployment with a mixture of host CPU models
+between machines, if live migration compatibility is required, use the newest
+CPU model that is compatible across all desired hosts.
+
address@hidden @option
address@hidden @code{Skylake-Server}
address@hidden @code{Skylake-Server-IBRS}
+
+Intel Xeon Processor (Skylake, 2016)
+
+
address@hidden @code{Skylake-Client}
address@hidden @code{Skylake-Client-IBRS}
+
+Intel Core Processor (Skylake, 2015)
+
+
address@hidden @code{Broadwell}
address@hidden @code{Broadwell-IBRS}
address@hidden @code{Broadwell-noTSX}
address@hidden @code{Broadwell-noTSX-IBRS}
+
+Intel Core Processor (Broadwell, 2014)
+
+
address@hidden @code{Haswell}
address@hidden @code{Haswell-IBRS}
address@hidden @code{Haswell-noTSX}
address@hidden @code{Haswell-noTSX-IBRS}
+
+Intel Core Processor (Haswell, 2013)
+
+
address@hidden @code{IvyBridge}
address@hidden @code{IvyBridge-IBRS}
+
+Intel Xeon E3-12xx v2 (Ivy Bridge, 2012)
+
+
address@hidden @code{SandyBridge}
address@hidden @code{SandyBridge-IBRS}
+
+Intel Xeon E312xx (Sandy Bridge, 2011)
+
+
address@hidden @code{Westmere}
address@hidden @code{Westmere-IBRS}
+
+Westmere E56xx/L56xx/X56xx (Nehalem-C, 2010)
+
+
address@hidden @code{Nehalem}
address@hidden @code{Nehalem-IBRS}
+
+Intel Core i7 9xx (Nehalem Class Core i7, 2008)
+
+
address@hidden @code{Penryn}
+
+Intel Core 2 Duo P9xxx (Penryn Class Core 2, 2007)
+
+
address@hidden @code{Conroe}
+
+Intel Celeron_4x0 (Conroe/Merom Class Core 2, 2006)
+
address@hidden table
+
address@hidden important_cpu_features_intel_x86
address@hidden Important CPU features for Intel x86 hosts
+
+The following are important CPU features that should be used on Intel x86
+hosts, when available in the host CPU. Some of them require explicit
+configuration to enable, as they are not included by default in some, or all,
+of the named CPU models listed above. In general all of these features are
+included if using "Host passthrough" or "Host model".
+
+
address@hidden @option
+
address@hidden @code{pcid}
+
+Recommended to mitigate the cost of the Meltdown (CVE-2017-5754) fix
+
+Included by default in Haswell, Broadwell & Skylake Intel CPU models.
+
+Should be explicitly turned on for Westmere, SandyBridge, and IvyBridge
+Intel CPU models. Note that some desktop/mobile Westmere CPUs cannot
+support this feature.
+
+
address@hidden @code{spec-ctrl}
+
+Required to enable the Spectre (CVE-2017-5753 and CVE-2017-5715) fix,
+in cases where retpolines are not sufficient.
+
+Included by default in Intel CPU models with -IBRS suffix.
+
+Must be explicitly turned on for Intel CPU models without -IBRS suffix.
+
+Requires the host CPU microcode to support this feature before it
+can be used for guest CPUs.
+
+
address@hidden @code{ssbd}
+
+Required to enable the CVE-2018-3639 fix
+
+Not included by default in any Intel CPU model.
+
+Must be explicitly turned on for all Intel CPU models.
+
+Requires the host CPU microcode to support this feature before it
+can be used for guest CPUs.
+
+
address@hidden @code{pdpe1gb}
+
+Recommended to allow guest OS to use 1GB size pages
+
+Not included by default in any Intel CPU model.
+
+Should be explicitly turned on for all Intel CPU models.
+
+Note that not all CPU hardware will support this feature.
address@hidden table
+
+
address@hidden preferred_cpu_models_amd_x86
address@hidden Preferred CPU models for AMD x86 hosts
+
+The following CPU models are preferred for use on Intel hosts. Administrators /
+applications are recommended to use the CPU model that matches the generation
+of the host CPUs in use. In a deployment with a mixture of host CPU models
+between machines, if live migration compatibility is required, use the newest
+CPU model that is compatible across all desired hosts.
+
address@hidden @option
+
address@hidden @code{EPYC}
address@hidden @code{EPYC-IBPB}
+
+AMD EPYC Processor (2017)
+
+
address@hidden @code{Opteron_G5}
+
+AMD Opteron 63xx class CPU (2012)
+
+
address@hidden @code{Opteron_G4}
+
+AMD Opteron 62xx class CPU (2011)
+
+
address@hidden @code{Opteron_G3}
+
+AMD Opteron 23xx (Gen 3 Class Opteron, 2009)
+
+
address@hidden @code{Opteron_G2}
+
+AMD Opteron 22xx (Gen 2 Class Opteron, 2006)
+
+
address@hidden @code{Opteron_G1}
+
+AMD Opteron 240 (Gen 1 Class Opteron, 2004)
address@hidden table
+
address@hidden important_cpu_features_amd_x86
address@hidden Important CPU features for AMD x86 hosts
+
+The following are important CPU features that should be used on AMD x86
+hosts, when available in the host CPU. Some of them require explicit
+configuration to enable, as they are not included by default in some, or all,
+of the named CPU models listed above. In general all of these features are
+included if using "Host passthrough" or "Host model".
+
+
address@hidden @option
+
address@hidden @code{ibpb}
+
+Required to enable the Spectre (CVE-2017-5753 and CVE-2017-5715) fix,
+in cases where retpolines are not sufficient.
+
+Included by default in AMD CPU models with -IBPB suffix.
+
+Must be explicitly turned on for AMD CPU models without -IBPB suffix.
+
+Requires the host CPU microcode to support this feature before it
+can be used for guest CPUs.
+
+
address@hidden @code{virt-ssbd}
+
+Required to enable the CVE-2018-3639 fix
+
+Not included by default in any AMD CPU model.
+
+Must be explicitly turned on for all AMD CPU models.
+
+This should be provided to guests, even if amd-ssbd is also
+provided, for maximum guest compatibility.
+
+Note for some QEMU / libvirt versions, this must be force enabled
+when when using "Host model", because this is a virtual feature
+that doesn't exist in the physical host CPUs.
+
+
address@hidden @code{amd-ssbd}
+
+Required to enable the CVE-2018-3639 fix
+
+Not included by default in any AMD CPU model.
+
+Must be explicitly turned on for all AMD CPU models.
+
+This provides higher performance than virt-ssbd so should be
+exposed to guests whenever available in the host. virt-ssbd
+should none the less also be exposed for maximum guest
+compatability as some kernels only know about virt-ssbd.
+
+
address@hidden @code{amd-no-ssb}
+
+Recommended to indicate the host is not vulnerable CVE-2018-3639
+
+Not included by default in any AMD CPU model.
+
+Future hardware genarations of CPU will not be vulnerable to
+CVE-2018-3639, and thus the guest should be told not to enable
+its mitigations, by exposing amd-no-ssb. This is mutually
+exclusive with virt-ssbd and amd-ssbd.
+
+
address@hidden @code{pdpe1gb}
+
+Recommended to allow guest OS to use 1GB size pages
+
+Not included by default in any AMD CPU model.
+
+Should be explicitly turned on for all AMD CPU models.
+
+Note that not all CPU hardware will support this feature.
address@hidden table
+
+
address@hidden default_cpu_models_x86
address@hidden Default x86 CPU models
+
+The default QEMU CPU models are designed such that they can run on all hosts.
+If an application does not wish to do perform any host compatibility checks
+before launching guests, the default is guaranteed to work.
+
+The default CPU models will, however, leave the guest OS vulnerable to various
+CPU hardware flaws, so their use is strongly discouraged. Applications should
+follow the earlier guidance to setup a better CPU configuration, with host
+passthrough recommended if live migration is not needed.
+
address@hidden @option
address@hidden @code{qemu32}
address@hidden @code{qemu64}
+
+QEMU Virtual CPU version 2.5+ (32 & 64 bit variants)
+
+qemu64 is used for x86_64 guests and qemu32 is used for i686 guests, when no
+-cpu argument is given to QEMU, or no <cpu> is provided in libvirt XML.
address@hidden table
+
+
address@hidden other_non_recommended_cpu_models_x86
address@hidden Other non-recommended x86 CPUs
+
+The following CPUs models are compatible with most AMD and Intel x86 hosts, but
+their usage is discouraged, as they expose a very limited featureset, which
+prevents guests having optimal performance.
+
address@hidden @option
+
address@hidden @code{kvm32}
address@hidden @code{kvm64}
+
+Common KVM processor (32 & 64 bit variants)
+
+Legacy models just for historical compatibility with ancient QEMU versions.
+
+
address@hidden @code{486}
address@hidden @code{athlon}
address@hidden @code{phenom}
address@hidden @code{coreduo}
address@hidden @code{core2duo}
address@hidden @code{n270}
address@hidden @code{pentium}
address@hidden @code{pentium2}
address@hidden @code{pentium3}
+
+Various very old x86 CPU models, mostly predating the introduction of
+hardware assisted virtualization, that should thus not be required for
+running virtual machines.
address@hidden table
+
address@hidden cpu_model_syntax_apps
address@hidden Syntax for configuring CPU models
+
+The example below illustrate the approach to configuring the various
+CPU models / features in QEMU and libvirt
+
address@hidden cpu_model_syntax_qemu
address@hidden QEMU command line
+
address@hidden @option
+
address@hidden Host passthrough
+
address@hidden
+   $ qemu-system-x86_64 -cpu host
address@hidden example
+
+With feature customization:
+
address@hidden
+   $ qemu-system-x86_64 -cpu host,-vmx,...
address@hidden example
+
address@hidden Named CPU models
+
address@hidden
+   $ qemu-system-x86_64 -cpu Westmere
address@hidden example
+
+With feature customization:
+
address@hidden
+   $ qemu-system-x86_64 -cpu Westmere,+pcid,...
address@hidden example
+
address@hidden table
+
address@hidden cpu_model_syntax_libvirt
address@hidden Libvirt guest XML
+
address@hidden @option
+
address@hidden Host passthrough
+
address@hidden
+   <cpu mode='host-passthrough'/>
address@hidden example
+
+With feature customization:
+
address@hidden
+   <cpu mode='host-passthrough'>
+       <feature name="vmx" policy="disable"/>
+       ...
+   </cpu>
address@hidden example
+
address@hidden Host model
+
address@hidden
+   <cpu mode='host-model'/>
address@hidden example
+
+With feature customization:
+
address@hidden
+   <cpu mode='host-model'>
+       <feature name="vmx" policy="disable"/>
+       ...
+   </cpu>
address@hidden example
+
address@hidden Named model
+
address@hidden
+   <cpu mode='custom'>
+       <model name="Westmere"/>
+   </cpu>
address@hidden example
+
+With feature customization:
+
address@hidden
+   <cpu mode='custom'>
+       <model name="Westmere"/>
+       <feature name="pcid" policy="require"/>
+       ...
+   </cpu>
address@hidden example
+
address@hidden table
+
address@hidden man end
+
address@hidden
+
address@hidden qemu-cpu-models
address@hidden QEMU / KVM CPU model configuration
+
address@hidden man begin SEEALSO
+The HTML documentation of QEMU for more precise information and Linux
+user mode emulator invocation.
address@hidden man end
+
address@hidden man begin AUTHOR
+Daniel P. Berrange
address@hidden man end
+
address@hidden ignore
diff --git a/qemu-doc.texi b/qemu-doc.texi
index cd05760cac..329689bdd1 100644
--- a/qemu-doc.texi
+++ b/qemu-doc.texi
@@ -602,6 +602,11 @@ The monitor understands integers expressions for every 
integer
 argument. You can use register names to get the value of specifics
 CPU registers by prefixing them with @emph{$}.
 
address@hidden cpu_models
address@hidden CPU models
+
address@hidden docs/qemu-cpu-models.texi
+
 @node disk_images
 @section Disk Images
 
-- 
2.17.0