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[Qemu-devel] [PATCH 085/113] hw/intc/arm_gicv3: Fix APxR<n> register dis
From: |
Michael Roth |
Subject: |
[Qemu-devel] [PATCH 085/113] hw/intc/arm_gicv3: Fix APxR<n> register dispatching |
Date: |
Mon, 18 Jun 2018 20:42:51 -0500 |
From: Jan Kiszka <address@hidden>
There was a nasty flip in identifying which register group an access is
targeting. The issue caused spuriously raised priorities of the guest
when handing CPUs over in the Jailhouse hypervisor.
Cc: address@hidden
Signed-off-by: Jan Kiszka <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
(cherry picked from commit 887aae10f6150dfdc71c45d7588e8efe6c144019)
Signed-off-by: Michael Roth <address@hidden>
---
hw/intc/arm_gicv3_cpuif.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index 5cbafaf497..519d581bb6 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -431,7 +431,7 @@ static uint64_t icv_ap_read(CPUARMState *env, const
ARMCPRegInfo *ri)
{
GICv3CPUState *cs = icc_cs_from_env(env);
int regno = ri->opc2 & 3;
- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
+ int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
uint64_t value = cs->ich_apr[grp][regno];
trace_gicv3_icv_ap_read(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
@@ -443,7 +443,7 @@ static void icv_ap_write(CPUARMState *env, const
ARMCPRegInfo *ri,
{
GICv3CPUState *cs = icc_cs_from_env(env);
int regno = ri->opc2 & 3;
- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
+ int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
trace_gicv3_icv_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs),
value);
@@ -1465,7 +1465,7 @@ static uint64_t icc_ap_read(CPUARMState *env, const
ARMCPRegInfo *ri)
uint64_t value;
int regno = ri->opc2 & 3;
- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1;
+ int grp = (ri->crm & 1) ? GICV3_G1 : GICV3_G0;
if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) {
return icv_ap_read(env, ri);
@@ -1487,7 +1487,7 @@ static void icc_ap_write(CPUARMState *env, const
ARMCPRegInfo *ri,
GICv3CPUState *cs = icc_cs_from_env(env);
int regno = ri->opc2 & 3;
- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1;
+ int grp = (ri->crm & 1) ? GICV3_G1 : GICV3_G0;
if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) {
icv_ap_write(env, ri, value);
@@ -2296,7 +2296,7 @@ static uint64_t ich_ap_read(CPUARMState *env, const
ARMCPRegInfo *ri)
{
GICv3CPUState *cs = icc_cs_from_env(env);
int regno = ri->opc2 & 3;
- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
+ int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
uint64_t value;
value = cs->ich_apr[grp][regno];
@@ -2309,7 +2309,7 @@ static void ich_ap_write(CPUARMState *env, const
ARMCPRegInfo *ri,
{
GICv3CPUState *cs = icc_cs_from_env(env);
int regno = ri->opc2 & 3;
- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
+ int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
trace_gicv3_ich_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs),
value);
--
2.11.0
- [Qemu-devel] [PATCH 078/113] pc-bios/s390-ccw: struct tpi_info must be declared as aligned(4), (continued)
- [Qemu-devel] [PATCH 078/113] pc-bios/s390-ccw: struct tpi_info must be declared as aligned(4), Michael Roth, 2018/06/18
- [Qemu-devel] [PATCH 079/113] qdev: rename typedef qdev_resetfn() -> DeviceReset(), Michael Roth, 2018/06/18
- [Qemu-devel] [PATCH 077/113] s390x/css: disabled subchannels cannot be status pending, Michael Roth, 2018/06/18
- [Qemu-devel] [PATCH 076/113] raw: Check byte range uniformly, Michael Roth, 2018/06/18
- [Qemu-devel] [PATCH 080/113] qdev: add helpers to be more explicit when using abstract QOM parent functions, Michael Roth, 2018/06/18
- [Qemu-devel] [PATCH 007/113] spapr: Adjust default VSMT value for better migration compatibility, Michael Roth, 2018/06/18
- [Qemu-devel] [PATCH 081/113] s390x/virtio: Convert virtio-ccw from *_exit to *_unrealize, Michael Roth, 2018/06/18
- [Qemu-devel] [PATCH 082/113] virtio-ccw: common reset handler, Michael Roth, 2018/06/18
- [Qemu-devel] [PATCH 083/113] s390x/ccw: make sure all ccw devices are properly reset, Michael Roth, 2018/06/18
- [Qemu-devel] [PATCH 084/113] console: Avoid segfault in screendump, Michael Roth, 2018/06/18
- [Qemu-devel] [PATCH 085/113] hw/intc/arm_gicv3: Fix APxR<n> register dispatching,
Michael Roth <=
- [Qemu-devel] [PATCH 088/113] intel-iommu: send PSI always even if across PDEs, Michael Roth, 2018/06/18
- [Qemu-devel] [PATCH 087/113] intel-iommu: Extend address width to 48 bits, Michael Roth, 2018/06/18
- [Qemu-devel] [PATCH 086/113] intel-iommu: Redefine macros to enable supporting 48 bit address width, Michael Roth, 2018/06/18
- [Qemu-devel] [PATCH 089/113] intel-iommu: remove IntelIOMMUNotifierNode, Michael Roth, 2018/06/18
- [Qemu-devel] [PATCH 008/113] spapr: set vsmt to MAX(8, smp_threads), Michael Roth, 2018/06/18
- [Qemu-devel] [PATCH 090/113] intel-iommu: add iommu lock, Michael Roth, 2018/06/18
- [Qemu-devel] [PATCH 092/113] intel-iommu: introduce vtd_page_walk_info, Michael Roth, 2018/06/18
- [Qemu-devel] [PATCH 093/113] intel-iommu: pass in address space when page walk, Michael Roth, 2018/06/18
- [Qemu-devel] [PATCH 094/113] intel-iommu: trace domain id during page walk, Michael Roth, 2018/06/18
- [Qemu-devel] [PATCH 091/113] intel-iommu: only do page walk for MAP notifiers, Michael Roth, 2018/06/18