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[Qemu-devel] [PATCH 24/35] target/mips: Add nanoMIPS CP0_BadInstrX regis
From: |
Yongbok Kim |
Subject: |
[Qemu-devel] [PATCH 24/35] target/mips: Add nanoMIPS CP0_BadInstrX register |
Date: |
Wed, 20 Jun 2018 13:06:09 +0100 |
From: Stefan Markovic <address@hidden>
Add nanoMIPS CP0_BadInstrX register
Signed-off-by: Stefan Markovic <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>
---
target/mips/cpu.h | 1 +
target/mips/helper.c | 6 ++++++
target/mips/machine.c | 1 +
target/mips/translate.c | 18 ++++++++++++++++++
4 files changed, 26 insertions(+)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 18f193d..c87184f 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -323,6 +323,7 @@ struct CPUMIPSState {
target_ulong CP0_BadVAddr;
uint32_t CP0_BadInstr;
uint32_t CP0_BadInstrP;
+ uint32_t CP0_BadInstrX;
int32_t CP0_Count;
target_ulong CP0_EntryHi;
#define CP0EnHi_EHINV 10
diff --git a/target/mips/helper.c b/target/mips/helper.c
index 5299f21..9535131 100644
--- a/target/mips/helper.c
+++ b/target/mips/helper.c
@@ -695,6 +695,12 @@ static inline void set_badinstr_registers(CPUMIPSState
*env)
instr |= cpu_lduw_code(env, env->active_tc.PC + 2);
}
env->CP0_BadInstr = instr;
+
+ if ((env->insn_flags & ISA_NANOMIPS32) &&
+ ((instr & 0xFC000000) == 0x60000000)) {
+ instr = cpu_lduw_code(env, env->active_tc.PC + 4) << 16;
+ env->CP0_BadInstrX = instr;
+ }
}
if ((env->CP0_Config3 & (1 << CP0C3_BP)) &&
(env->hflags & MIPS_HFLAG_BMASK)) {
diff --git a/target/mips/machine.c b/target/mips/machine.c
index 20100d5..58f3255 100644
--- a/target/mips/machine.c
+++ b/target/mips/machine.c
@@ -266,6 +266,7 @@ const VMStateDescription vmstate_mips_cpu = {
VMSTATE_UINTTL(env.CP0_BadVAddr, MIPSCPU),
VMSTATE_UINT32(env.CP0_BadInstr, MIPSCPU),
VMSTATE_UINT32(env.CP0_BadInstrP, MIPSCPU),
+ VMSTATE_UINT32(env.CP0_BadInstrX, MIPSCPU),
VMSTATE_INT32(env.CP0_Count, MIPSCPU),
VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU),
VMSTATE_INT32(env.CP0_Compare, MIPSCPU),
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 8c20ba3..ece2293 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -5429,6 +5429,11 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrP));
rn = "BadInstrP";
break;
+ case 3:
+ CP0_CHECK(ctx->bi);
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrX));
+ rn = "BadInstrX";
+ break;
default:
goto cp0_unimplemented;
}
@@ -6098,6 +6103,10 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
/* ignored */
rn = "BadInstrP";
break;
+ case 3:
+ /* ignored */
+ rn = "BadInstrX";
+ break;
default:
goto cp0_unimplemented;
}
@@ -6781,6 +6790,11 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrP));
rn = "BadInstrP";
break;
+ case 3:
+ CP0_CHECK(ctx->bi);
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrX));
+ rn = "BadInstrX";
+ break;
default:
goto cp0_unimplemented;
}
@@ -7433,6 +7447,10 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
/* ignored */
rn = "BadInstrP";
break;
+ case 3:
+ /* ignored */
+ rn = "BadInstrX";
+ break;
default:
goto cp0_unimplemented;
}
--
1.9.1
- [Qemu-devel] [PATCH 16/35] target/mips: Add has_isa_mode, (continued)
- [Qemu-devel] [PATCH 16/35] target/mips: Add has_isa_mode, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 17/35] target/mips: Add nanoMIPS load store instructions, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 18/35] target/mips: Add nanoMIPS branch instructions, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 19/35] target/mips: Implement nanoMIPS LLWP/SCWP pair, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 20/35] target/mips: Fix not to update BadVAddr in Debug Mode, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 21/35] target/mips: Add nanoMIPS rotx instruction, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 22/35] target/mips: Fix data type for offset, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 23/35] target/mips: Update BadInstr{P} regs on nanoMIPS, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 24/35] target/mips: Add nanoMIPS CP0_BadInstrX register,
Yongbok Kim <=
- [Qemu-devel] [PATCH 25/35] target/mips: Config3.ISAOnExc is read only in nanoMIPS, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 26/35] target/mips: Fix nanoMIPS exception_resume_pc, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 27/35] target/mips: Fix nanoMIPS set_hflags_for_handler, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 28/35] target/mips: Fix nanoMIPS set_pc, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 29/35] target/mips: Fix ERET/ERETNC can cause ADEL exception, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 30/35] hw/mips: Add basic nanoMIPS boot code, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 31/35] mips_malta: Setup GT64120 BARs in nanoMIPS bootloader, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 32/35] hw/mips: Fix semihosting argument passing for nanoMIPS bare metal, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 33/35] target/mips: Fix gdbstub to read/write 64 bit FP registers, Yongbok Kim, 2018/06/20