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[Qemu-devel] [PATCH v5 12/35] target/arm: Implement SVE prefetches
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v5 12/35] target/arm: Implement SVE prefetches |
Date: |
Wed, 20 Jun 2018 15:53:36 -1000 |
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate-sve.c | 21 +++++++++++++++++++++
target/arm/sve.decode | 23 +++++++++++++++++++++++
2 files changed, 44 insertions(+)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 6e1907cedd..c054e3268b 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -4302,3 +4302,24 @@ static bool trans_ST1_zprz(DisasContext *s, arg_ST1_zprz
*a, uint32_t insn)
cpu_reg_sp(s, a->rn), fn);
return true;
}
+
+/*
+ * Prefetches
+ */
+
+static bool trans_PRF(DisasContext *s, arg_PRF *a, uint32_t insn)
+{
+ /* Prefetch is a nop within QEMU. */
+ sve_access_check(s);
+ return true;
+}
+
+static bool trans_PRF_rr(DisasContext *s, arg_PRF_rr *a, uint32_t insn)
+{
+ if (a->rm == 31) {
+ return false;
+ }
+ /* Prefetch is a nop within QEMU. */
+ sve_access_check(s);
+ return true;
+}
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index 2ca0fd85e6..a20f98b70c 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -793,6 +793,29 @@ LD1RQ_zprr 1010010 .. 00 ..... 000 ... ..... ..... \
LD1RQ_zpri 1010010 .. 00 0.... 001 ... ..... ..... \
@rpri_load_msz nreg=0
+# SVE 32-bit gather prefetch (scalar plus 32-bit scaled offsets)
+PRF 1000010 00 -1 ----- 0-- --- ----- 0 ----
+
+# SVE 32-bit gather prefetch (vector plus immediate)
+PRF 1000010 -- 00 ----- 111 --- ----- 0 ----
+
+# SVE contiguous prefetch (scalar plus immediate)
+PRF 1000010 11 1- ----- 0-- --- ----- 0 ----
+
+# SVE contiguous prefetch (scalar plus scalar)
+PRF_rr 1000010 -- 00 rm:5 110 --- ----- 0 ----
+
+### SVE Memory 64-bit Gather Group
+
+# SVE 64-bit gather prefetch (scalar plus 64-bit scaled offsets)
+PRF 1100010 00 11 ----- 1-- --- ----- 0 ----
+
+# SVE 64-bit gather prefetch (scalar plus unpacked 32-bit scaled offsets)
+PRF 1100010 00 -1 ----- 0-- --- ----- 0 ----
+
+# SVE 64-bit gather prefetch (vector plus immediate)
+PRF 1100010 -- 00 ----- 111 --- ----- 0 ----
+
### SVE Memory Store Group
# SVE store predicate register
--
2.17.1
- Re: [Qemu-devel] [PATCH v5 07/35] target/arm: Implement SVE FP Multiply-Add Group, (continued)
[Qemu-devel] [PATCH v5 08/35] target/arm: Implement SVE Floating Point Accumulating Reduction Group, Richard Henderson, 2018/06/20
[Qemu-devel] [PATCH v5 09/35] target/arm: Implement SVE load and broadcast element, Richard Henderson, 2018/06/20
[Qemu-devel] [PATCH v5 10/35] target/arm: Implement SVE store vector/predicate register, Richard Henderson, 2018/06/20
[Qemu-devel] [PATCH v5 12/35] target/arm: Implement SVE prefetches,
Richard Henderson <=
[Qemu-devel] [PATCH v5 13/35] target/arm: Implement SVE gather loads, Richard Henderson, 2018/06/20
[Qemu-devel] [PATCH v5 11/35] target/arm: Implement SVE scatter stores, Richard Henderson, 2018/06/20
[Qemu-devel] [PATCH v5 15/35] target/arm: Implement SVE scatter store vector immediate, Richard Henderson, 2018/06/20
[Qemu-devel] [PATCH v5 14/35] target/arm: Implement SVE first-fault gather loads, Richard Henderson, 2018/06/20