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Re: [Qemu-devel] [PATCH v2 00/22] target/openrisc improvements

From: Stafford Horne
Subject: Re: [Qemu-devel] [PATCH v2 00/22] target/openrisc improvements
Date: Thu, 21 Jun 2018 20:00:53 +0900
User-agent: Mutt/1.9.5 (2018-04-13)

On Mon, Jun 18, 2018 at 08:40:24AM -1000, Richard Henderson wrote:
> This is almost a grab-bag of little improvements to the port.
> patches 1-3:
>   Fix singlestepping for gdbstub.  This has apparently never
>   worked, as the first commit has the same bug of not advancing
>   the pc when stepping.
> patches 4:
>   Link more TBs.
> patches 5-6:
>   Exit the TB after l.mtspr insns.  In particular, storing to
>   SR changes exception state so we want to return to the main
>   loop to recognize any pending interrupts immediately.
> patches 8-18:
>   Reorganize TLB handling.  There is a fundamental bug that is
>   fixed in patch 13.  However the bug has been hidden by extra
>   TLB flushing elsewhere in the port.  I remove some unnecessary
>   indirection that the port inherited from somewhere -- probably
>   the MIPS port.  Finally, I present the QEMU TLB a unified view
>   of the OpenRISC split I/D TLB.
> patch 19:
>   Split out disassembly from translation.
> patch 20:
>   Add qemu-or1k to qemu-binfmt-conf.sh.
> patches 21-22:
>   Implement signal handling for linux-user.

Hi Richard,

Thanks for these, I think there are a few white space issues throughout.  Do you
mind if I take these and clean them up (indent with space) and work on the DSX
and Interrupt issue I mentioned earlier?

I can submit all during the next merge window.

Let me know if you have other plans or you think they can go right away.


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