[Top][All Lists]

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [Qemu-devel] [PATCH v2 7/7] xlnx-zynqmp: Improve GIC wiring and MMIO

From: Peter Maydell
Subject: Re: [Qemu-devel] [PATCH v2 7/7] xlnx-zynqmp: Improve GIC wiring and MMIO mapping
Date: Mon, 25 Jun 2018 15:29:04 +0100

On 19 June 2018 at 10:31,  <address@hidden> wrote:
> From: Luc MICHEL <address@hidden>
> This commit improve the way the GIC is realized and connected in the
> ZynqMP SoC. The security extensions are enabled only if requested in the
> machine state. The same goes for the virtualization extensions.
> All the GIC to APU CPU(s) IRQ lines are now connected, including FIQ,
> vIRQ and vFIQ. The missing CPU to GIC timers IRQ connections are also
> added (HYP and SEC timers).
> The GIC maintenance IRQs are back-wired to the correct GIC PPIs.
> Finally, the MMIO mappings are reworked to take into account the ZynqMP
> specificities. the GIC (v)CPU interface is aliased 16 times:
>   * for the firsts 0x1000 bytes from 0xf9010000 to 0xf901f000
>   * for the seconds 0x1000 bytes from 0xf9020000 to 0xf902f000
> Mappings of the virtual interface and virtual CPU interface are mapped
> only when virtualization extensions are requested. The
> XlnxZynqMPGICRegion struct has been enhanced to be able to catch all
> this information.
> Signed-off-by: Luc MICHEL <address@hidden>
> ---
>  hw/arm/xlnx-zynqmp.c         | 92 ++++++++++++++++++++++++++++++++----
>  include/hw/arm/xlnx-zynqmp.h |  4 +-
>  2 files changed, 86 insertions(+), 10 deletions(-)

Nothing obviously wrong-looking in here; a review from one of
the Xilinx folk would be good.

-- PMM

reply via email to

[Prev in Thread] Current Thread [Next in Thread]