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[Qemu-devel] [PULL 03/12] i386: improve sorting of CPU model names
From: |
Eduardo Habkost |
Subject: |
[Qemu-devel] [PULL 03/12] i386: improve sorting of CPU model names |
Date: |
Mon, 25 Jun 2018 19:25:15 -0300 |
From: Daniel P. Berrangé <address@hidden>
The current list of CPU model names output by "-cpu help" is sorted
alphabetically based on the internal QOM class name. The text that is
displayed, however, uses the CPU model name, which is equivalent to the
QOM class name, minus a suffix. Unfortunately that suffix has an effect
on the sort ordering, for example, causing the various Broadwell
variants to appear reversed:
x86 486
x86 Broadwell-IBRS Intel Core Processor (Broadwell, IBRS)
x86 Broadwell-noTSX-IBRS Intel Core Processor (Broadwell, no TSX, IBRS
x86 Broadwell-noTSX Intel Core Processor (Broadwell, no TSX)
x86 Broadwell Intel Core Processor (Broadwell)
x86 Conroe Intel Celeron_4x0 (Conroe/Merom Class Core 2)
By sorting on the actual CPU model name text that is displayed, the
result is
x86 486
x86 Broadwell Intel Core Processor (Broadwell)
x86 Broadwell-IBRS Intel Core Processor (Broadwell, IBRS)
x86 Broadwell-noTSX Intel Core Processor (Broadwell, no TSX)
x86 Broadwell-noTSX-IBRS Intel Core Processor (Broadwell, no TSX, IBRS)
x86 Conroe Intel Celeron_4x0 (Conroe/Merom Class Core 2)
This requires extra string allocations during sorting, but this is not a
concern given the usage scenario and the number of CPU models that exist.
Signed-off-by: Daniel P. Berrangé <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>
---
target/i386/cpu.c | 14 +++++++++-----
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index e1d7157d8c..19ac1e6569 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3351,15 +3351,19 @@ static gint x86_cpu_list_compare(gconstpointer a,
gconstpointer b)
ObjectClass *class_b = (ObjectClass *)b;
X86CPUClass *cc_a = X86_CPU_CLASS(class_a);
X86CPUClass *cc_b = X86_CPU_CLASS(class_b);
- const char *name_a, *name_b;
+ char *name_a, *name_b;
+ int ret;
if (cc_a->ordering != cc_b->ordering) {
- return cc_a->ordering - cc_b->ordering;
+ ret = cc_a->ordering - cc_b->ordering;
} else {
- name_a = object_class_get_name(class_a);
- name_b = object_class_get_name(class_b);
- return strcmp(name_a, name_b);
+ name_a = x86_cpu_class_get_model_name(cc_a);
+ name_b = x86_cpu_class_get_model_name(cc_b);
+ ret = strcmp(name_a, name_b);
+ g_free(name_a);
+ g_free(name_b);
}
+ return ret;
}
static GSList *get_sorted_cpu_model_list(void)
--
2.18.0.rc1.1.g3f1ff2140
- [Qemu-devel] [PULL 00/12] x86 queue, 2018-06-25, Eduardo Habkost, 2018/06/25
- [Qemu-devel] [PULL 01/12] i386: Add support for CPUID_8000_001E for AMD, Eduardo Habkost, 2018/06/25
- [Qemu-devel] [PULL 02/12] i386: improve alignment of CPU model listing, Eduardo Habkost, 2018/06/25
- [Qemu-devel] [PULL 03/12] i386: improve sorting of CPU model names,
Eduardo Habkost <=
- [Qemu-devel] [PULL 04/12] i386: display known CPUID features linewrapped, in alphabetical order, Eduardo Habkost, 2018/06/25
- [Qemu-devel] [PULL 05/12] i386: Remove osxsave CPUID flag name, Eduardo Habkost, 2018/06/25
- [Qemu-devel] [PULL 06/12] i386: Remove ospke CPUID flag name, Eduardo Habkost, 2018/06/25
- [Qemu-devel] [PULL 07/12] i386: define the AMD 'amd-ssbd' CPUID feature bit, Eduardo Habkost, 2018/06/25
- [Qemu-devel] [PULL 08/12] i386: Define AMD's no SSB mitigation needed., Eduardo Habkost, 2018/06/25
- [Qemu-devel] [PULL 09/12] i386: Allow TOPOEXT to be enabled on older kernels, Eduardo Habkost, 2018/06/25
- [Qemu-devel] [PULL 10/12] i386: Fix up the Node id for CPUID_8000_001E, Eduardo Habkost, 2018/06/25
- [Qemu-devel] [PULL 11/12] i386: Enable TOPOEXT feature on AMD EPYC CPU, Eduardo Habkost, 2018/06/25
- [Qemu-devel] [PULL 12/12] i386: Remove generic SMT thread check, Eduardo Habkost, 2018/06/25
- Re: [Qemu-devel] [PULL 00/12] x86 queue, 2018-06-25, Peter Maydell, 2018/06/26