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Re: [Qemu-devel] [PATCH v5 01/35] target/arm: Implement SVE Memory Conti
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH v5 01/35] target/arm: Implement SVE Memory Contiguous Load Group |
Date: |
Tue, 26 Jun 2018 07:04:03 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.8.0 |
On 06/26/2018 02:55 AM, Alex Bennée wrote:
>> +/* Convert a 2-bit memory size (msz) to a 4-bit data type (dtype)
>> + * with unsigned data. C.f. SVE Memory Contiguous Load Group.
>> + */
>> +static inline int msz_dtype(int msz)
>> +{
>> + static const uint8_t dtype[4] = { 0, 5, 10, 15 };
>> + return dtype[msz];
>> +}
> I'm a little confused by the magic numbers in dtype[4], do they map
> directly to dtype_mop[]?
>
Well, yes, this would sort of be the inverse of dtype_mop.
My intent with the comment was to point you to the table within
the SVE Memory - Contiguous Load Group section of
the Index by Encoding page:
DDI0584A_d_SVE/SVE_xml/xhtml/encodingindex.html#sve_memcld
and that I'm picking out the unsigned loads of size 1, 2, 4, 8.
Do you have a suggested re-wording?
I should note that *most* load operations use a 4-bit dtype field, except for
the non-temporal loads, which use a 2-bit msz field. Since qemu does not care
about the memory hierarchy, by mapping msz back into dtype I can forward the
implementation directly to the normal load routines.
r~