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Re: [Qemu-devel] [PATCH v5 13/35] target/arm: Implement SVE gather loads
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH v5 13/35] target/arm: Implement SVE gather loads |
Date: |
Tue, 26 Jun 2018 07:39:14 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.8.0 |
On 06/25/2018 09:55 AM, Peter Maydell wrote:
>> +static bool trans_LD1_zprz(DisasContext *s, arg_LD1_zprz *a, uint32_t insn)
>> +{
>> + gen_helper_gvec_mem_scatter *fn = NULL;
>> +
>> + if (a->esz < a->msz
>> + || (a->msz == 0 && a->scale)
> Doesn't this check duplicate work you're already doing in the decode
> entries in the .decode file? If we're going to throw out msz==0 scale==1
> here we don't need to go to the effort to split this into 4 patterns
> so we can force the scale bit to 0 in the msz=00 line:
>
>> +LD1_zprz 1100010 00 .0 ..... 0.. ... ..... ..... \
>> + @rprr_g_load_xs_u esz=3 msz=0 scale=0
>> +LD1_zprz 1100010 01 .. ..... 0.. ... ..... ..... \
>> + @rprr_g_load_xs_u_sc esz=3 msz=1
>> +LD1_zprz 1100010 10 .. ..... 0.. ... ..... ..... \
>> + @rprr_g_load_xs_u_sc esz=3 msz=2
>> +LD1_zprz 1100010 11 .. ..... 0.. ... ..... ..... \
>> + @rprr_g_load_xs_u_sc esz=3 msz=3
> and could just have
> LD1_zprz 1100010 msz:2 .. ..... 0.. ... ..... ..... \
> @rprr_g_load_xs_u_sc esz=3 scale=0
>
> couldn't we?
>
> (I don't really care which way round we do it.)
>
I believe that I originally had the combined form, but it conflicts with some
other pattern (looking through the patterns, perhaps PRF?). I must have
squashed the patch to split the pattern without removing the check in the
helper.
> Is LDFF1 support going to appear later in this patchset?
>
> For the moment should we UNDEF it?
Next patch, as you found. Maybe I'll just drop the comment from this patch. I
may also re-format the tables here, so they don't require so much re-formatting
in the next patch.
r~
- Re: [Qemu-devel] [PATCH v5 08/35] target/arm: Implement SVE Floating Point Accumulating Reduction Group, (continued)
- [Qemu-devel] [PATCH v5 09/35] target/arm: Implement SVE load and broadcast element, Richard Henderson, 2018/06/20
- [Qemu-devel] [PATCH v5 10/35] target/arm: Implement SVE store vector/predicate register, Richard Henderson, 2018/06/20
- [Qemu-devel] [PATCH v5 12/35] target/arm: Implement SVE prefetches, Richard Henderson, 2018/06/20
- [Qemu-devel] [PATCH v5 13/35] target/arm: Implement SVE gather loads, Richard Henderson, 2018/06/20
- [Qemu-devel] [PATCH v5 11/35] target/arm: Implement SVE scatter stores, Richard Henderson, 2018/06/20
- [Qemu-devel] [PATCH v5 15/35] target/arm: Implement SVE scatter store vector immediate, Richard Henderson, 2018/06/20
- [Qemu-devel] [PATCH v5 14/35] target/arm: Implement SVE first-fault gather loads, Richard Henderson, 2018/06/20
- [Qemu-devel] [PATCH v5 16/35] target/arm: Implement SVE floating-point compare vectors, Richard Henderson, 2018/06/20