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[Qemu-devel] [PATCH v3 10/23] target/openrisc: Form the spr index from t
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v3 10/23] target/openrisc: Form the spr index from tcg |
Date: |
Wed, 27 Jun 2018 20:03:17 -0700 |
Rather than pass base+offset to the helper, pass the full index.
In most cases the base is r0 and optimization yields a constant.
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/openrisc/helper.h | 4 ++--
target/openrisc/sys_helper.c | 9 +++------
target/openrisc/translate.c | 16 +++++++++-------
3 files changed, 14 insertions(+), 15 deletions(-)
diff --git a/target/openrisc/helper.h b/target/openrisc/helper.h
index e37dabc77a..9db9bf3963 100644
--- a/target/openrisc/helper.h
+++ b/target/openrisc/helper.h
@@ -56,5 +56,5 @@ FOP_CMP(le)
DEF_HELPER_FLAGS_1(rfe, 0, void, env)
/* sys */
-DEF_HELPER_FLAGS_4(mtspr, 0, void, env, tl, tl, tl)
-DEF_HELPER_FLAGS_4(mfspr, TCG_CALL_NO_WG, tl, env, tl, tl, tl)
+DEF_HELPER_FLAGS_3(mtspr, 0, void, env, tl, tl)
+DEF_HELPER_FLAGS_3(mfspr, TCG_CALL_NO_WG, tl, env, tl, tl)
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index 2f337363ec..2c959f63f4 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -27,13 +27,11 @@
#define TO_SPR(group, number) (((group) << 11) + (number))
-void HELPER(mtspr)(CPUOpenRISCState *env,
- target_ulong ra, target_ulong rb, target_ulong offset)
+void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
{
#ifndef CONFIG_USER_ONLY
OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
CPUState *cs = CPU(cpu);
- int spr = (ra | offset);
int idx;
switch (spr) {
@@ -202,13 +200,12 @@ void HELPER(mtspr)(CPUOpenRISCState *env,
#endif
}
-target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
- target_ulong rd, target_ulong ra, uint32_t offset)
+target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd,
+ target_ulong spr)
{
#ifndef CONFIG_USER_ONLY
OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
CPUState *cs = CPU(cpu);
- int spr = (ra | offset);
int idx;
switch (spr) {
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 59605aacca..64b5e84630 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -865,9 +865,10 @@ static bool trans_l_mfspr(DisasContext *dc, arg_l_mfspr
*a, uint32_t insn)
if (is_user(dc)) {
gen_illegal_exception(dc);
} else {
- TCGv_i32 ti = tcg_const_i32(a->k);
- gen_helper_mfspr(cpu_R[a->d], cpu_env, cpu_R[a->d], cpu_R[a->a], ti);
- tcg_temp_free_i32(ti);
+ TCGv spr = tcg_temp_new();
+ tcg_gen_ori_tl(spr, cpu_R[a->a], a->k);
+ gen_helper_mfspr(cpu_R[a->d], cpu_env, cpu_R[a->d], spr);
+ tcg_temp_free(spr);
}
return true;
}
@@ -877,7 +878,7 @@ static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a,
uint32_t insn)
if (is_user(dc)) {
gen_illegal_exception(dc);
} else {
- TCGv_i32 ti;
+ TCGv spr;
/* For SR, we will need to exit the TB to recognize the new
* exception state. For NPC, in theory this counts as a branch
@@ -892,9 +893,10 @@ static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr
*a, uint32_t insn)
}
dc->base.is_jmp = DISAS_EXIT;
- ti = tcg_const_i32(a->k);
- gen_helper_mtspr(cpu_env, cpu_R[a->a], cpu_R[a->b], ti);
- tcg_temp_free_i32(ti);
+ spr = tcg_temp_new();
+ tcg_gen_ori_tl(spr, cpu_R[a->a], a->k);
+ gen_helper_mtspr(cpu_env, spr, cpu_R[a->b]);
+ tcg_temp_free(spr);
}
return true;
}
--
2.17.1
- [Qemu-devel] [PATCH v3 00/23] target/openrisc improvements, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 01/23] target/openrisc: Fix mtspr shadow gprs, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 03/23] target/openrisc: Log interrupts, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 04/23] target/openrisc: Remove DISAS_JUMP & DISAS_TB_JUMP, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 05/23] target/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTB, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 06/23] target/openrisc: Fix singlestep_enabled, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 10/23] target/openrisc: Form the spr index from tcg,
Richard Henderson <=
- [Qemu-devel] [PATCH v3 02/23] target/openrisc: Add print_insn_or1k, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 07/23] target/openrisc: Link more translation blocks, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 08/23] target/openrisc: Split out is_user, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 12/23] target/openrisc: Remove indirect function calls for mmu, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 11/23] target/openrisc: Merge tlb allocation into CPUOpenRISCState, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 09/23] target/openrisc: Exit the TB after l.mtspr, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 14/23] target/openrisc: Reduce tlb to a single dimension, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 16/23] target/openrisc: Fix cpu_mmu_index, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 13/23] target/openrisc: Merge mmu_helper.c into mmu.c, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 15/23] target/openrisc: Fix tlb flushing in mtspr, Richard Henderson, 2018/06/27