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Re: [Qemu-devel] [PATCH 02/13] target/ppc: Use atomic load for LQ and LQ

From: Richard Henderson
Subject: Re: [Qemu-devel] [PATCH 02/13] target/ppc: Use atomic load for LQ and LQARX
Date: Thu, 28 Jun 2018 08:22:38 -0700
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.8.0

On 06/27/2018 08:49 PM, David Gibson wrote:
>> +    /* High part of 128-bit helper return.  */
>> +    uint64_t retxh;
>> +
> Adding a temporary here is kind of gross.  I guess the helper
> interface doesn't allow for 128-bit returns, but couldn't you pass a
> register number into the helper and have it update the right GPR
> without going through a temp?

I could pass a pointer, but that would cause ...

>> +#if defined(TARGET_PPC64) && defined(CONFIG_ATOMIC128)
>> +DEF_HELPER_FLAGS_3(lq_le_parallel, TCG_CALL_NO_WG, i64, env, tl, i32)
>> +DEF_HELPER_FLAGS_3(lq_be_parallel, TCG_CALL_NO_WG, i64, env, tl, i32)

... the helper definitions to lose TCG_CALL_NO_WG, because they *would* write
to a global register.  Which would cause TCG to discard all of the global guest
registers cached within host registers.

I've used this secondary memory return before, in target/s390,
and to me it seems cleaner than pointers.


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