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[Qemu-devel] [PATCH for-3.0] accel/tcg: Don't treat invalid TLB entries
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH for-3.0] accel/tcg: Don't treat invalid TLB entries as needing recheck |
Date: |
Fri, 29 Jun 2018 17:17:31 +0100 |
In get_page_addr_code() when we check whether the TLB entry
is marked as TLB_RECHECK, we should not go down that code
path if the TLB entry is not valid at all (ie the TLB_INVALID
bit is set).
Reported-by: Laurent Vivier <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
This fixes the abort that Laurent was seeing with his m68k test case.
accel/tcg/cputlb.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index eebe97dabb7..a55296583b9 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -967,7 +967,8 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env,
target_ulong addr)
}
}
- if (unlikely(env->tlb_table[mmu_idx][index].addr_code & TLB_RECHECK)) {
+ if (unlikely((env->tlb_table[mmu_idx][index].addr_code &
+ (TLB_RECHECK | TLB_INVALID_MASK)) == TLB_RECHECK)) {
/*
* This is a TLB_RECHECK access, where the MMU protection
* covers a smaller range than a target page, and we must
--
2.17.1
- [Qemu-devel] [PATCH for-3.0] accel/tcg: Don't treat invalid TLB entries as needing recheck,
Peter Maydell <=