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Re: [Qemu-devel] OpenRISC - SPR_PICMR always 'OR-ing' the values

From: Davidson Francis
Subject: Re: [Qemu-devel] OpenRISC - SPR_PICMR always 'OR-ing' the values
Date: Sun, 1 Jul 2018 15:30:00 -0300
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.8.0


Thanks for working on this, your tree works fine here and the issue
seems to be fixed, I have nothing to complain about.

Davidson Francis.

On 01-07-2018 05:18, Stafford Horne wrote:

We have been working on a few patches to fixed QEMU for OpenRISC and I
included the change for picmr writes, richard added some changes to
SPR writes which might help with the masking/umasking work more

If you want to try them out could you check:

Thanks for your help.


On Sun, May 20, 2018 at 12:32 PM Davidson Francis
<address@hidden> wrote:

Thank you for quick reply,

Yes, I've tried, after that, the register works as expected, but even so, if I
enable the interrupts right after, I still receive interrupts from the same IRQ,
but maybe there is something wrong with my code.

Davidson Francis.

2018-05-19 23:54 GMT-03:00 Stafford Horne <address@hidden>:
On Sat, May 19, 2018 at 08:08:47PM -0300, Davidson Francis wrote:
Hello Stafford,

I'm currently using or1k as a target CPU in an operating system that
I'm working.
It happens that I'm having some issues regarding the PICMR register: I realize
that in the latest Qemu version (2.12) when I write into PICMR, the Qemu is
actually 'OR-ing' the values (as I could note in target/openrisc/sys_helper.c
file), so I can't mask an already enabled interrupt.

I don't know if this behaviour is expected and if so, I'm sorry, but this does
not occurs in the or1ksim, so I thought this could be might an issue.

Hello, thanks for pointing this out.  It looks wrong to me too.  Have you tested
changing it to just `env->picmr = rb;`?


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