Re: [Qemu-devel] [PULL v4 0/7] riscv-pull queue

[Peter Maydell]

On 6 July 2018 at 02:22, Alistair Francis <address@hidden> wrote:
> The following changes since commit cee35138b59c6d6b0808c5fa644e3f063832860f:
>
>   Merge remote-tracking branch 
> 'remotes/stsquad/tags/pull-code-coverage-and-build-tweaks-050718-3' into 
> staging (2018-07-05 18:24:28 +0100)
>
> are available in the Git repository at:
>
>   address@hidden:alistair23/qemu.git tags/pull-riscv-pull-20180705
>
> for you to fetch changes up to 5a7f76a3d47a75290868968682c0585d380764a4:
>
>   hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device (2018-07-05 
> 15:24:25 -0700)
>
> ----------------------------------------------------------------
> RISC-V: SoCify SiFive boards and connect GEM
>
> This series has three tasks:
>  1. To convert the SiFive U and E machines into SoCs and boards
>  2. To connect the Cadence GEM device to the SiFive U board
>  3. Fix some device tree problems with the SiFive U board
>
> After this series the SiFive E and U boards have their SoCs split into
> seperate QEMU objects, which can be used on future boards if desired.
>
> The RISC-V Virt and Spike boards have not been converted. They haven't
> been converted as they aren't physical boards, so it doesn't make a
> whole lot of sense to split them into an SoC and board. The only
> disadvantage with this is that they now differ to the SiFive boards.
>
> This series also connect the Cadence GEM device to the SiFive U board.
> There are some interrupt line changes requried before this is possible.

Applied, thanks.

-- PMM