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Re: [Qemu-devel] [PATCH v3 1/2] nvic: Handle ARMv6-M SCS reserved regist

From: Peter Maydell
Subject: Re: [Qemu-devel] [PATCH v3 1/2] nvic: Handle ARMv6-M SCS reserved registers
Date: Fri, 6 Jul 2018 16:05:58 +0100

On 5 July 2018 at 23:21, Julia Suvorova <address@hidden> wrote:
> Handle SCS reserved registers listed in ARMv6-M ARM D3.6.1.
> All reserved registers are RAZ/WI. ARM_FEATURE_M_MAIN is used for the
> checks, because these registers are reserved in ARMv8-M Baseline too.
> Signed-off-by: Julia Suvorova <address@hidden>
> ---
>  hw/intc/armv7m_nvic.c | 51 +++++++++++++++++++++++++++++++++++++++++--
>  1 file changed, 49 insertions(+), 2 deletions(-)

Reviewed-by: Peter Maydell <address@hidden>

I've applied this patch (but not the 2nd one in this series)
to target-arm.for-3.1.

-- PMM

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