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Re: [Qemu-devel] [PULL 4/6] accel/tcg: Don't treat invalid TLB entries a

From: Peter Maydell
Subject: Re: [Qemu-devel] [PULL 4/6] accel/tcg: Don't treat invalid TLB entries as needing recheck
Date: Fri, 13 Jul 2018 13:50:23 +0100

On 13 July 2018 at 13:36, Richard Henderson
<address@hidden> wrote:
> On 07/13/2018 06:05 AM, Peter Maydell wrote:
>>> -    if (unlikely(env->tlb_table[mmu_idx][index].addr_code & TLB_RECHECK)) {
>>> +    if (unlikely((env->tlb_table[mmu_idx][index].addr_code &
>>> +                  (TLB_RECHECK | TLB_INVALID_MASK)) == TLB_RECHECK)) {
>>>          /*
>>>           * This is a TLB_RECHECK access, where the MMU protection
>>>           * covers a smaller range than a target page, and we must
>> Looking again at this code, I think that now we have the code to
>> ensure that there's only ever one entry in the TLB/victim TLB for
>> a given guest address...
> Which probably wasn't the case the first time you wrote this, no?
> Fixing that single entry condition was just a few weeks ago.

Yes, exactly.

OTOH with Laurent's m68k test case I'm finding that the assert
is firing, and I'm not entirely sure why yet...

-- PMM

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