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[Qemu-devel] [PULL 3/8] hw/intc/arm_gic: Check interrupt number in gic_d
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 3/8] hw/intc/arm_gic: Check interrupt number in gic_deactivate_irq() |
Date: |
Mon, 16 Jul 2018 17:42:55 +0100 |
In gic_deactivate_irq() the interrupt number comes from the guest
(on a write to the GICC_DIR register), so we need to sanity check
that it isn't out of range before we use it as an array index.
Handle this in a similar manner to the check we do in
gic_complete_irq() for the GICC_EOI register.
The array overrun is not disastrous because the calling code
uses (value & 0x3ff) to extract the interrupt field, so the
only out-of-range values possible are 1020..1023, which allow
overrunning only from irq_state[] into the following
irq_target[] array which the guest can already manipulate.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Luc Michel <address@hidden>
Message-id: address@hidden
---
hw/intc/arm_gic.c | 16 +++++++++++++++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index ea0323f9691..b0a69d6386e 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -543,7 +543,21 @@ static bool gic_eoi_split(GICState *s, int cpu, MemTxAttrs
attrs)
static void gic_deactivate_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
{
int cm = 1 << cpu;
- int group = gic_has_groups(s) && GIC_TEST_GROUP(irq, cm);
+ int group;
+
+ if (irq >= s->num_irq) {
+ /*
+ * This handles two cases:
+ * 1. If software writes the ID of a spurious interrupt [ie 1023]
+ * to the GICC_DIR, the GIC ignores that write.
+ * 2. If software writes the number of a non-existent interrupt
+ * this must be a subcase of "value written is not an active interrupt"
+ * and so this is UNPREDICTABLE. We choose to ignore it.
+ */
+ return;
+ }
+
+ group = gic_has_groups(s) && GIC_TEST_GROUP(irq, cm);
if (!gic_eoi_split(s, cpu, attrs)) {
/* This is UNPREDICTABLE; we choose to ignore it */
--
2.17.1
- [Qemu-devel] [PULL 0/8] target-arm queue, Peter Maydell, 2018/07/16
- [Qemu-devel] [PULL 3/8] hw/intc/arm_gic: Check interrupt number in gic_deactivate_irq(),
Peter Maydell <=
- [Qemu-devel] [PULL 4/8] hw/intc/arm_gic: Fix handling of GICD_ITARGETSR, Peter Maydell, 2018/07/16
- [Qemu-devel] [PULL 2/8] aspeed: Implement write-1-{set, clear} for AST2500 strapping, Peter Maydell, 2018/07/16
- [Qemu-devel] [PULL 1/8] target/arm: Fix LD1W and LDFF1W (scalar plus vector), Peter Maydell, 2018/07/16
- [Qemu-devel] [PULL 5/8] hw/arm/bcm2836: Mark the bcm2836 / bcm2837 devices with user_creatable = false, Peter Maydell, 2018/07/16
- [Qemu-devel] [PULL 8/8] accel/tcg: Assert that tlb fill gave us a valid TLB entry, Peter Maydell, 2018/07/16
- [Qemu-devel] [PULL 6/8] bcm2835_aux: Swap RX and TX interrupt assignments, Peter Maydell, 2018/07/16
- [Qemu-devel] [PULL 7/8] accel/tcg: Use correct test when looking in victim TLB for code, Peter Maydell, 2018/07/16
- Re: [Qemu-devel] [PULL 0/8] target-arm queue, Peter Maydell, 2018/07/17