[Top][All Lists]

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [Qemu-devel] [PATCH] accel/tcg: Check whether TLB entry is RAM consi

From: Peter Maydell
Subject: Re: [Qemu-devel] [PATCH] accel/tcg: Check whether TLB entry is RAM consistently with how we set it up
Date: Tue, 24 Jul 2018 13:26:34 +0100

On 15 July 2018 at 01:37, Richard Henderson <address@hidden> wrote:
> On 07/13/2018 10:09 AM, Peter Maydell wrote:
>> @@ -939,29 +935,21 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env, 
>> target_ulong addr)
>>          }
>>          assert(tlb_hit(env->tlb_table[mmu_idx][index].addr_code, addr));
>>      }
>> +    assert(tlb_hit(env->tlb_table[mmu_idx][index].addr_code, addr));
> Don't duplicate the assert; just move it.  Otherwise,
> Reviewed-by: Richard Henderson <address@hidden>

I propose to put this patch into my target-arm.for-3.1 branch
(with the duplicated assert deleted), unless you have another

-- PMM

reply via email to

[Prev in Thread] Current Thread [Next in Thread]