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[Qemu-devel] [PATCH v4 11/55] target/mips: Add emulation of nanoMIPS 48-
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PATCH v4 11/55] target/mips: Add emulation of nanoMIPS 48-bit instructions |
Date: |
Tue, 24 Jul 2018 19:31:23 +0200 |
From: Yongbok Kim <address@hidden>
Add emulation of LI48, ADDIU48, ADDIUGP48, ADDIUPC48, LWPC48, and
SWPC48 instructions.
Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Stefan Markovic <address@hidden>
Reviewed-by: Aleksandar Markovic <address@hidden>
---
target/mips/translate.c | 66 +++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 66 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 0b69ceb..f5f722d 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -16684,6 +16684,72 @@ static int decode_nanomips_32_48_opc(CPUMIPSState
*env, DisasContext *ctx)
}
break;
case NM_P48I:
+ insn = cpu_lduw_code(env, ctx->base.pc_next + 4);
+ switch ((ctx->opcode >> 16) & 0x1f) {
+ case NM_LI48:
+ if (rt != 0) {
+ tcg_gen_movi_tl(cpu_gpr[rt],
+ extract32(ctx->opcode, 0, 16) | insn << 16);
+ }
+ break;
+ case NM_ADDIU48:
+ if (rt != 0) {
+ tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rt],
+ extract32(ctx->opcode, 0, 16) | insn << 16);
+ tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
+ }
+ break;
+ case NM_ADDIUGP48:
+ if (rt != 0) {
+ tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[28],
+ extract32(ctx->opcode, 0, 16) | insn << 16);
+ tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
+ }
+ break;
+ case NM_ADDIUPC48:
+ if (rt != 0) {
+ int32_t offset = extract32(ctx->opcode, 0, 16) | insn << 16;
+ target_long addr = addr_add(ctx, ctx->base.pc_next + 6,
offset);
+
+ tcg_gen_movi_tl(cpu_gpr[rt], addr);
+ tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
+ }
+ break;
+ case NM_LWPC48:
+ if (rt != 0) {
+ TCGv t0;
+ t0 = tcg_temp_new();
+
+ int32_t offset = extract32(ctx->opcode, 0, 16) | insn << 16;
+ target_long addr = addr_add(ctx, ctx->base.pc_next + 6,
offset);
+
+ tcg_gen_movi_tl(t0, addr);
+ tcg_gen_qemu_ld_tl(cpu_gpr[rt], t0, ctx->mem_idx, MO_TESL);
+ tcg_temp_free(t0);
+ }
+ break;
+ case NM_SWPC48:
+ {
+ TCGv t0, t1;
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new();
+
+ int32_t offset = extract32(ctx->opcode, 0, 16) | insn << 16;
+ target_long addr = addr_add(ctx, ctx->base.pc_next + 6,
offset);
+
+ tcg_gen_movi_tl(t0, addr);
+ gen_load_gpr(t1, rt);
+
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ }
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
return 6;
case NM_P_U12:
switch ((ctx->opcode >> 12) & 0x0f) {
--
2.7.4
- [Qemu-devel] [PATCH v4 05/55] target/mips: Add nanoMIPS decoding and extraction utilities, (continued)
- [Qemu-devel] [PATCH v4 05/55] target/mips: Add nanoMIPS decoding and extraction utilities, Aleksandar Markovic, 2018/07/24
- [Qemu-devel] [PATCH v4 06/55] target/mips: Add emulation of misc nanoMIPS 16-bit instructions, Aleksandar Markovic, 2018/07/24
- [Qemu-devel] [PATCH v4 07/55] target/mips: Add emulation of nanoMIPS 16-bit load and store instructions, Aleksandar Markovic, 2018/07/24
- [Qemu-devel] [PATCH v4 08/55] target/mips: Add emulation of nanoMIPS 16-bit logic instructions, Aleksandar Markovic, 2018/07/24
- [Qemu-devel] [PATCH v4 09/55] target/mips: Add emulation of nanoMIPS 16-bit save and restore instructions, Aleksandar Markovic, 2018/07/24
- [Qemu-devel] [PATCH v4 10/55] target/mips: Add emulation of some common nanoMIPS 32-bit instructions, Aleksandar Markovic, 2018/07/24
- [Qemu-devel] [PATCH v4 11/55] target/mips: Add emulation of nanoMIPS 48-bit instructions,
Aleksandar Markovic <=
- [Qemu-devel] [PATCH v4 12/55] target/mips: Add emulation of nanoMIPS FP instructions, Aleksandar Markovic, 2018/07/24
- [Qemu-devel] [PATCH v4 13/55] target/mips: Add emulation of misc nanoMIPS instructions (pool32a0), Aleksandar Markovic, 2018/07/24
- [Qemu-devel] [PATCH v4 14/55] target/mips: Add emulation of misc nanoMIPS instructions (pool32axf), Aleksandar Markovic, 2018/07/24
- [Qemu-devel] [PATCH v4 15/55] target/mips: Add emulation of misc nanoMIPS instructions (pool p_lsx), Aleksandar Markovic, 2018/07/24
- [Qemu-devel] [PATCH v4 16/55] target/mips: Implement emulation of nanoMIPS ROTX instruction, Aleksandar Markovic, 2018/07/24
- [Qemu-devel] [PATCH v4 17/55] target/mips: Implement emulation of nanoMIPS EXTW instruction, Aleksandar Markovic, 2018/07/24
- [Qemu-devel] [PATCH v4 18/55] target/mips: Add emulation of nanoMIPS 32-bit load and store instructions, Aleksandar Markovic, 2018/07/24
- [Qemu-devel] [PATCH v4 19/55] target/mips: Add emulation of nanoMIPS branch instructions, Aleksandar Markovic, 2018/07/24
- [Qemu-devel] [PATCH v4 20/55] target/mips: Implement MT ASE support for nanoMIPS, Aleksandar Markovic, 2018/07/24
- [Qemu-devel] [PATCH v4 21/55] target/mips: Add emulation of DSP ASE for nanoMIPS - part 1, Aleksandar Markovic, 2018/07/24