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[Qemu-devel] [PATCH v1 4/4] target/riscv: set mtval and stval support
From: |
Alistair Francis |
Subject: |
[Qemu-devel] [PATCH v1 4/4] target/riscv: set mtval and stval support |
Date: |
Wed, 25 Jul 2018 16:04:25 -0700 |
Signed-off-by: Alistair Francis <address@hidden>
---
target/riscv/cpu.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d630e8fd6c..b33950a2d4 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -133,6 +133,8 @@ static void rv32gcsu_priv1_10_0_cpu_init(Object *obj)
set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0);
set_resetvec(env, DEFAULT_RSTVEC);
set_feature(env, RISCV_FEATURE_MMU);
+ set_feature(env, RISCV_FEATURE_MTVAL_INST);
+ set_feature(env, RISCV_FEATURE_STVAL_INST);
}
static void rv32imacu_nommu_cpu_init(Object *obj)
@@ -161,6 +163,8 @@ static void rv64gcsu_priv1_10_0_cpu_init(Object *obj)
set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0);
set_resetvec(env, DEFAULT_RSTVEC);
set_feature(env, RISCV_FEATURE_MMU);
+ set_feature(env, RISCV_FEATURE_MTVAL_INST);
+ set_feature(env, RISCV_FEATURE_STVAL_INST);
}
static void rv64imacu_nommu_cpu_init(Object *obj)
--
2.17.1