[Top][All Lists]

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [Qemu-devel] [Qemu-arm] [PATCH v3 4/7] target/arm: add "cortex-m0" C

From: Peter Maydell
Subject: Re: [Qemu-devel] [Qemu-arm] [PATCH v3 4/7] target/arm: add "cortex-m0" CPU model
Date: Mon, 30 Jul 2018 18:51:27 +0100

On 27 July 2018 at 06:26, Philippe Mathieu-Daudé <address@hidden> wrote:
> Hi Stefan,
> On 07/25/2018 05:59 AM, Stefan Hajnoczi wrote:
>> Define a "cortex-m0" ARMv6-M CPU model.
>> Most of the register reset values set by other CPU models are not
>> relevant for the cut-down ARMv6-M architecture.
>> Signed-off-by: Stefan Hajnoczi <address@hidden>
>> ---
>>  target/arm/cpu.c | 11 +++++++++++
>>  1 file changed, 11 insertions(+)
>> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
>> index 3848ef46aa..7e477c0d23 100644
>> --- a/target/arm/cpu.c
>> +++ b/target/arm/cpu.c
>> @@ -1255,6 +1255,15 @@ static void arm11mpcore_initfn(Object *obj)
>>      cpu->reset_auxcr = 1;
>>  }
>> +static void cortex_m0_initfn(Object *obj)
>> +{
>> +    ARMCPU *cpu = ARM_CPU(obj);
>> +    set_feature(&cpu->env, ARM_FEATURE_V6);
>> +    set_feature(&cpu->env, ARM_FEATURE_M);
> What about ARM_FEATURE_THUMB2 (T32)?

No, the M0 doesn't have Thumb2. It has Thumb1 plus a tiny set
of 32-bit instructions (which we deal with specially in translate.c).

(As it happens we generally can't get to the checks on the THUMB2
feature for a v6M core, so I think but have not checked thoroughly
that it would make no difference to QEMU's behaviour whether the
feature bit was set or not.)

> Peter: Since the M0 (optionally?) supports 32x32 multiply, should this
> cpu use the ARM_FEATURE_THUMB_DSP feature? Else this might trigger an
> 'Undefined Instruction' in disas_thumb2_insn().

ARM_FEATURE_THUMB_DSP only enables checks in disas_thumb2_insn()
(and 32x32->32 multiply is not one of the insns it gates).
The only insns in that function that a v6M core can execute are
msr, mrs, dsb, dmb, isb and bl, none of which are affected by that
feature switch.

> And what about optional ARM_FEATURE_PMSA?
> Oh this would be cortex_m0plus_initfn() for "cortex-m0-plus", ok.

Yep, plain M0 has no MPU (and so we're postponing the work
of implementing the v6M PMSA, which IIRC isn't quite the
same as the v7M one).

-- PMM

reply via email to

[Prev in Thread] Current Thread [Next in Thread]