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Re: [Qemu-devel] [PATCH 1/6] target/arm: Adjust FPCR_MASK for FZ16
From: |
Laurent Desnogues |
Subject: |
Re: [Qemu-devel] [PATCH 1/6] target/arm: Adjust FPCR_MASK for FZ16 |
Date: |
Sat, 11 Aug 2018 18:22:33 +0200 |
On Fri, Aug 10, 2018 at 9:31 PM, Richard Henderson
<address@hidden> wrote:
> When support for FZ16 was added, we failed to include the bit
> within FPCR_MASK, which means that it could never be set.
> Continue to zero FZ16 when ARMv8.2-FP16 is not enabled.
>
> Fixes: d81ce0ef2c4
> Cc: address@hidden (3.0.1)
> Reported-by: Laurent Desnogues <address@hidden>
> Signed-off-by: Richard Henderson <address@hidden>
Tested-by: Laurent Desnogues <address@hidden>
Reviewed-by: Laurent Desnogues <address@hidden>
Laurent
> ---
> target/arm/cpu.h | 2 +-
> target/arm/helper.c | 5 +++++
> 2 files changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index 33d06f2340..0176716a70 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -1279,7 +1279,7 @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val);
> * we store the underlying state in fpscr and just mask on read/write.
> */
> #define FPSR_MASK 0xf800009f
> -#define FPCR_MASK 0x07f79f00
> +#define FPCR_MASK 0x07ff9f00
>
> #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */
> #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 64ff71b722..452d5e182a 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -11351,6 +11351,11 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env,
> uint32_t val)
> int i;
> uint32_t changed;
>
> + /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */
> + if (!arm_feature(env, ARM_FEATURE_V8_FP16)) {
> + val &= ~FPCR_FZ16;
> + }
> +
> changed = env->vfp.xregs[ARM_VFP_FPSCR];
> env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
> env->vfp.vec_len = (val >> 16) & 7;
> --
> 2.17.1
>
- [Qemu-devel] [PATCH 0/6] target/arm: More sve-ish fixes, Richard Henderson, 2018/08/10
- [Qemu-devel] [PATCH 1/6] target/arm: Adjust FPCR_MASK for FZ16, Richard Henderson, 2018/08/10
- Re: [Qemu-devel] [PATCH 1/6] target/arm: Adjust FPCR_MASK for FZ16,
Laurent Desnogues <=
- [Qemu-devel] [PATCH 2/6] target/arm: Ignore float_flag_input_denormal from fp_status_f16, Richard Henderson, 2018/08/10
- [Qemu-devel] [PATCH 3/6] target/arm: Use fp_status_fp16 for do_fmpa_zpzzz_h, Richard Henderson, 2018/08/10
- [Qemu-devel] [PATCH 5/6] target/arm: Fix aa64 FCADD and FCMLA decode, Richard Henderson, 2018/08/10
- [Qemu-devel] [PATCH 4/6] target/arm: Use FZ not FZ16 for SVE FCVT single-half and double-half, Richard Henderson, 2018/08/10
- [Qemu-devel] [PATCH 6/6] softfloat: Fix missing inexact for floating-point add, Richard Henderson, 2018/08/10