Re: [Qemu-devel] [PATCH 03/10] target/arm: Implement RAZ/WI HACTLR2

[Luc Michel]

On 8/14/18 2:42 PM, Peter Maydell wrote:
> The AArch32 HACTLR2 register maps to bits [63:32] of ACTLR_EL2.
> We implement ACTLR_EL2 as RAZ/WI, so make HACTLR2 also RAZ/WI.
> (We put the regdef next to ACTLR_EL2 as a reminder in case we
> ever make ACTLR_EL2 something other than RAZ/WI).
Putting this regdef in the auxcr_reginfo[] array makes it defined when
the ARM_FEATURE_AUXCR is set (starting from ARM1026 ARMv5 I think).
However I believe this register only exists for ARMv8, for AArch32 mode
to be able to access upper bits of ACTLR_EL2. Should not we check for
ARM_FEATURE_ARMV8 being set so we don't define it for ARMv7?

-- 
Luc

> 
> Signed-off-by: Peter Maydell <address@hidden>
> ---
>  target/arm/helper.c | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 466c8ae492e..14fd78f587a 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -5436,6 +5436,11 @@ void register_cp_regs_for_features(ARMCPU *cpu)
>                .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1,
>                .access = PL2_RW, .type = ARM_CP_CONST,
>                .resetvalue = 0 },
> +            /* HACTLR2 maps to ACTLR_EL2[63:32] */
> +            { .name = "HACTLR2", .state = ARM_CP_STATE_AA32,
> +              .cp = 15, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 3,
> +              .access = PL2_RW, .type = ARM_CP_CONST,
> +              .resetvalue = 0 },
>              { .name = "ACTLR_EL3", .state = ARM_CP_STATE_AA64,
>                .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1,
>                .access = PL3_RW, .type = ARM_CP_CONST,
>

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