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Re: [Qemu-devel] [PATCH v9 40/84] target/mips: Fix pre-nanoMIPS MT ASE i

From: Richard Henderson
Subject: Re: [Qemu-devel] [PATCH v9 40/84] target/mips: Fix pre-nanoMIPS MT ASE instructions availability control
Date: Thu, 16 Aug 2018 09:37:18 -0700
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1

On 08/16/2018 07:57 AM, Aleksandar Markovic wrote:
> From: Aleksandar Rikalo <address@hidden>
> Use bits from configuration registers for availability control
> of MT ASE instructions, rather than only ISA_MT bit in insn_flags.
> This is done by adding a field in hflags for MT bit, and adding
> functions check_mt() and check_cp0_mt().
> Reviewed-by: Aleksandar Markovic <address@hidden>
> Signed-off-by: Aleksandar Markovic <address@hidden>
> Signed-off-by: Stefan Markovic <address@hidden>
> ---
>  target/mips/cpu.h       |  3 ++-
>  target/mips/internal.h  |  6 +++++-
>  target/mips/translate.c | 45 +++++++++++++++++++++++++++++++++++++--------
>  3 files changed, 44 insertions(+), 10 deletions(-)

What was wrong with using insn_flags?

I'll note that hflags should be reserved for things that can change at runtime.
 I thought all of these configuration registers were read-only.

Anyway, with this plus the XNP patch from earlier, you now only have one
remaining bit within hflags and then that resource is exhausted.


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