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[Qemu-devel] [PATCH v10 21/65] target/mips: Implement emulation of nanoM
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PATCH v10 21/65] target/mips: Implement emulation of nanoMIPS EXTW instruction |
Date: |
Fri, 17 Aug 2018 16:03:09 +0200 |
From: James Hogan <address@hidden>
Implement emulation of nanoMIPS EXTW instruction. EXTW instruction
is similar to the MIPS r6 ALIGN instruction, except that it counts
the other way and in bits instead of bytes. We therefore generalise
gen_align() function into a new gen_align_bits() function (which
counts in bits instead of bytes and optimises when bits = size of
the word), and implement gen_align() and a new gen_ext() based on
that. Since we need to know the word size to check for when the
number of bits == the word size, the opc argument is replaced with
a wordsz argument (either 32 or 64).
Signed-off-by: James Hogan <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Stefan Markovic <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target/mips/translate.c | 53 +++++++++++++++++++++++++++++++++----------------
1 file changed, 36 insertions(+), 17 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 31aa242..2eccc89 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -4870,8 +4870,8 @@ static void gen_lsa(DisasContext *ctx, int opc, int rd,
int rs, int rt,
return;
}
-static void gen_align(DisasContext *ctx, int opc, int rd, int rs, int rt,
- int bp)
+static void gen_align_bits(DisasContext *ctx, int wordsz, int rd, int rs,
+ int rt, int bits)
{
TCGv t0;
if (rd == 0) {
@@ -4879,35 +4879,40 @@ static void gen_align(DisasContext *ctx, int opc, int
rd, int rs, int rt,
return;
}
t0 = tcg_temp_new();
- gen_load_gpr(t0, rt);
- if (bp == 0) {
- switch (opc) {
- case OPC_ALIGN:
+ if (bits == 0 || bits == wordsz) {
+ if (bits == 0) {
+ gen_load_gpr(t0, rt);
+ } else {
+ gen_load_gpr(t0, rs);
+ }
+ switch (wordsz) {
+ case 32:
tcg_gen_ext32s_tl(cpu_gpr[rd], t0);
break;
#if defined(TARGET_MIPS64)
- case OPC_DALIGN:
+ case 64:
tcg_gen_mov_tl(cpu_gpr[rd], t0);
break;
#endif
}
} else {
TCGv t1 = tcg_temp_new();
+ gen_load_gpr(t0, rt);
gen_load_gpr(t1, rs);
- switch (opc) {
- case OPC_ALIGN:
+ switch (wordsz) {
+ case 32:
{
TCGv_i64 t2 = tcg_temp_new_i64();
tcg_gen_concat_tl_i64(t2, t1, t0);
- tcg_gen_shri_i64(t2, t2, 8 * (4 - bp));
+ tcg_gen_shri_i64(t2, t2, 32 - bits);
gen_move_low32(cpu_gpr[rd], t2);
tcg_temp_free_i64(t2);
}
break;
#if defined(TARGET_MIPS64)
- case OPC_DALIGN:
- tcg_gen_shli_tl(t0, t0, 8 * bp);
- tcg_gen_shri_tl(t1, t1, 8 * (8 - bp));
+ case 64:
+ tcg_gen_shli_tl(t0, t0, bits);
+ tcg_gen_shri_tl(t1, t1, 64 - bits);
tcg_gen_or_tl(cpu_gpr[rd], t1, t0);
break;
#endif
@@ -4918,6 +4923,18 @@ static void gen_align(DisasContext *ctx, int opc, int
rd, int rs, int rt,
tcg_temp_free(t0);
}
+static void gen_align(DisasContext *ctx, int wordsz, int rd, int rs, int rt,
+ int bp)
+{
+ gen_align_bits(ctx, wordsz, rd, rs, rt, bp * 8);
+}
+
+static void gen_ext(DisasContext *ctx, int wordsz, int rd, int rs, int rt,
+ int shift)
+{
+ gen_align_bits(ctx, wordsz, rd, rs, rt, wordsz - shift);
+}
+
static void gen_bitswap(DisasContext *ctx, int opc, int rd, int rt)
{
TCGv t0;
@@ -14410,8 +14427,7 @@ static void decode_micromips32_opc(CPUMIPSState *env,
DisasContext *ctx)
break;
case ALIGN:
check_insn(ctx, ISA_MIPS32R6);
- gen_align(ctx, OPC_ALIGN, rd, rs, rt,
- extract32(ctx->opcode, 9, 2));
+ gen_align(ctx, 32, rd, rs, rt, extract32(ctx->opcode, 9, 2));
break;
case EXT:
gen_bitops(ctx, OPC_EXT, rt, rs, rr, rd);
@@ -17616,6 +17632,9 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env,
DisasContext *ctx)
gen_lsa(ctx, OPC_LSA, rd, rs, rt,
extract32(ctx->opcode, 9, 2) - 1);
break;
+ case NM_EXTW:
+ gen_ext(ctx, 32, rd, rs, rt, extract32(ctx->opcode, 6, 5));
+ break;
case NM_POOL32AXF:
gen_pool32axf_nanomips_insn(env, ctx);
break;
@@ -20463,7 +20482,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env,
DisasContext *ctx)
switch (op2) {
case OPC_ALIGN:
case OPC_ALIGN_END:
- gen_align(ctx, OPC_ALIGN, rd, rs, rt, sa & 3);
+ gen_align(ctx, 32, rd, rs, rt, sa & 3);
break;
case OPC_BITSWAP:
gen_bitswap(ctx, op2, rd, rt);
@@ -20489,7 +20508,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env,
DisasContext *ctx)
switch (op2) {
case OPC_DALIGN:
case OPC_DALIGN_END:
- gen_align(ctx, OPC_DALIGN, rd, rs, rt, sa & 7);
+ gen_align(ctx, 64, rd, rs, rt, sa & 7);
break;
case OPC_DBITSWAP:
gen_bitswap(ctx, op2, rd, rt);
--
2.7.4
- [Qemu-devel] [PATCH v10 46/65] linux-user: Add target_signal.h header for nanoMIPS, (continued)
- [Qemu-devel] [PATCH v10 46/65] linux-user: Add target_signal.h header for nanoMIPS, Aleksandar Markovic, 2018/08/17
- [Qemu-devel] [PATCH v10 49/65] linux-user: Add target_fcntl.h header for nanoMIPS, Aleksandar Markovic, 2018/08/17
- [Qemu-devel] [PATCH v10 48/65] linux-user: Update syscall_defs.h header for nanoMIPS, Aleksandar Markovic, 2018/08/17
- [Qemu-devel] [PATCH v10 16/65] target/mips: Add emulation of nanoMIPS FP instructions, Aleksandar Markovic, 2018/08/17
- [Qemu-devel] [PATCH v10 27/65] target/mips: Add emulation of DSP ASE for nanoMIPS - part 1, Aleksandar Markovic, 2018/08/17
- [Qemu-devel] [PATCH v10 38/65] elf: On elf loading, treat both EM_MIPS and EM_NANOMIPS as legal for MIPS, Aleksandar Markovic, 2018/08/17
- [Qemu-devel] [PATCH v10 35/65] target/mips: Fix ERET/ERETNC behavior related to ADEL exception, Aleksandar Markovic, 2018/08/17
- [Qemu-devel] [PATCH v10 63/65] gdbstub: Disable handling of nanoMIPS ISA bit in the MIPS gdbstub, Aleksandar Markovic, 2018/08/17
- [Qemu-devel] [PATCH v10 30/65] target/mips: Add emulation of DSP ASE for nanoMIPS - part 4, Aleksandar Markovic, 2018/08/17
- [Qemu-devel] [PATCH v10 20/65] target/mips: Implement emulation of nanoMIPS ROTX instruction, Aleksandar Markovic, 2018/08/17
- [Qemu-devel] [PATCH v10 21/65] target/mips: Implement emulation of nanoMIPS EXTW instruction,
Aleksandar Markovic <=
- [Qemu-devel] [PATCH v10 25/65] target/mips: Fix pre-nanoMIPS MT ASE instructions availability control, Aleksandar Markovic, 2018/08/17
- [Qemu-devel] [PATCH v10 55/65] linux-user: Add signal.c for nanoMIPS, Aleksandar Markovic, 2018/08/17
- [Qemu-devel] [PATCH v10 56/65] linux-user: Add support for nanoMIPS signal trampoline, Aleksandar Markovic, 2018/08/17
- [Qemu-devel] [PATCH v10 51/65] linux-user: Add target_syscall.h header for nanoMIPS, Aleksandar Markovic, 2018/08/17
- [Qemu-devel] [PATCH v10 58/65] linux-user: Amend support for sigaction() syscall for nanoMIPS, Aleksandar Markovic, 2018/08/17
- [Qemu-devel] [PATCH v10 43/65] target/mips: Add definition of nanoMIPS I7200 CPU, Aleksandar Markovic, 2018/08/17
- [Qemu-devel] [PATCH v10 62/65] linux-user: Add nanoMIPS support in scripts/qemu-binfmt-conf.sh, Aleksandar Markovic, 2018/08/17
- [Qemu-devel] [PATCH v10 23/65] target/mips: Implement emulation of nanoMIPS LLWP/SCWP pair, Aleksandar Markovic, 2018/08/17
- [Qemu-devel] [PATCH v10 24/65] target/mips: Add emulation of nanoMIPS 32-bit branch instructions, Aleksandar Markovic, 2018/08/17