Re: [Qemu-devel] [Qemu-arm] [PATCH 08/16] hw/misc/iotkit-secctl: Wire up registers for controlling MSCs

[Philippe Mathieu-Daudé]

On 08/18/2018 07:05 AM, Peter Maydell wrote:
> On 18 August 2018 at 01:37, Philippe Mathieu-Daudé <address@hidden> wrote:
>> On 08/09/2018 10:01 AM, Peter Maydell wrote:
>>> The IoTKit does not have any Master Security Contollers itself,
>>> but it does provide registers in the secure privilege control
>>> block which allow control of MSCs in the external system.
>>> Add support for these registers.
>>>
>>> Signed-off-by: Peter Maydell <address@hidden>
>>> ---
> 
>>>      case A_SECMSCINTEN:
>>> -        qemu_log_mask(LOG_UNIMP,
>>> -                      "IoTKit SecCtl S block write: "
>>> -                      "unimplemented offset 0x%x\n", offset);
>>
>> Maybe:
>>
>>            if (value & ~0xffff) {
>>                GUEST_ERROR(...)
>>            }
> 
> We don't generally bother to log writes of raz bits as errors.

Yes I know, and this shouldn't make sens for an well publicly documented
device/board as this IoT Kit.

But you would be surprised by some proprietary firmwares or libraries
provided by some companies...
I have been surprised modeling the Hercules TMS570 series from TI, they
provide a datasheet with the register/bits for the embedded Flash
(F021), and a library/API to access this flash, however when I ran
firmwares linked with their flash library I noticed they access
undocumented bits to restrict^H^H^H^H^configure their flash, and I had
to model those undocumented bits to allow the firmware to continue
further and boot.

So not needed for this model, but it may be sometime useful ;)

Regards,

Phil.