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[Qemu-devel] [PULL 24/46] target/mips: Add CP0 Config3 and Config5 field
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL 24/46] target/mips: Add CP0 Config3 and Config5 fields to DisasContext structure |
Date: |
Tue, 21 Aug 2018 14:35:29 +0200 |
From: Dimitrije Nikolic <address@hidden>
Add CP0_Config3 and CP0_Config5 to DisasContext structure. This is
needed for implementing availability control of various instructions.
Signed-off-by: "Aleksandar Markovic <address@hidden>"
---
target/mips/translate.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index a06b5b1..dc1760b 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1449,6 +1449,8 @@ typedef struct DisasContext {
uint32_t opcode;
int insn_flags;
int32_t CP0_Config1;
+ int32_t CP0_Config3;
+ int32_t CP0_Config5;
/* Routine used to access memory */
int mem_idx;
TCGMemOp default_tcg_memop_mask;
@@ -23305,6 +23307,8 @@ static void mips_tr_init_disas_context(DisasContextBase
*dcbase, CPUState *cs)
ctx->saved_pc = -1;
ctx->insn_flags = env->insn_flags;
ctx->CP0_Config1 = env->CP0_Config1;
+ ctx->CP0_Config3 = env->CP0_Config3;
+ ctx->CP0_Config5 = env->CP0_Config5;
ctx->btarget = 0;
ctx->kscrexist = (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff;
ctx->rxi = (env->CP0_Config3 >> CP0C3_RXI) & 1;
--
2.7.4
- [Qemu-devel] [PULL 00/46] MIPS queue August 21, 2018, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 09/46] target/mips: Add emulation of nanoMIPS 16-bit shift instructions, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 04/46] target/mips: Prevent switching mode related to Config3 ISA bit for nanoMIPS, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 03/46] target/mips: Add nanoMIPS DSP ASE opcodes, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 12/46] target/mips: Add emulation of nanoMIPS 16-bit logic instructions, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 06/46] target/mips: Add nanoMIPS decoding and extraction utilities, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 07/46] target/mips: Add emulation of nanoMIPS 16-bit arithmetic instructions, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 01/46] target/mips: Add preprocessor constants for nanoMIPS, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 27/46] target/mips: Fix pre-nanoMIPS MT ASE instructions availability control, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 24/46] target/mips: Add CP0 Config3 and Config5 fields to DisasContext structure,
Aleksandar Markovic <=
- [Qemu-devel] [PULL 40/46] elf: Relax MIPS' elf_check_arch() to accept EM_NANOMIPS too, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 20/46] target/mips: Add emulation of misc nanoMIPS instructions (p_lsx), Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 22/46] target/mips: Implement emulation of nanoMIPS EXTW instruction, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 02/46] target/mips: Add nanoMIPS base instruction set opcodes, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 19/46] target/mips: Add emulation of misc nanoMIPS instructions (pool32axf), Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 43/46] mips_malta: Add basic nanoMIPS boot code for Malta board, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 35/46] target/mips: Add availability control via bit NMS, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 15/46] target/mips: Add emulation of nanoMIPS instructions MOVE.P and MOVE.PREV, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 10/46] target/mips: Add emulation of nanoMIPS 16-bit misc instructions, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 05/46] target/mips: Add placeholder and invocation of decode_nanomips_opc(), Aleksandar Markovic, 2018/08/21