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[Qemu-devel] [PULL 10/46] target/mips: Add emulation of nanoMIPS 16-bit
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL 10/46] target/mips: Add emulation of nanoMIPS 16-bit misc instructions |
Date: |
Tue, 21 Aug 2018 14:35:15 +0200 |
From: Yongbok Kim <address@hidden>
Add emulation of misc nanoMIPS 16-bit instructions.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Stefan Markovic <address@hidden>
---
target/mips/translate.c | 41 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index e3fac1a..c774dc9 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -16763,6 +16763,40 @@ static int decode_nanomips_opc(CPUMIPSState *env,
DisasContext *ctx)
op = extract32(ctx->opcode, 10, 6);
switch (op) {
case NM_P16_MV:
+ rt = NANOMIPS_EXTRACT_RD5(ctx->opcode);
+ if (rt != 0) {
+ /* MOVE */
+ rs = NANOMIPS_EXTRACT_RS5(ctx->opcode);
+ gen_arith(ctx, OPC_ADDU, rt, rs, 0);
+ } else {
+ /* P16.RI */
+ switch (extract32(ctx->opcode, 3, 2)) {
+ case NM_P16_SYSCALL:
+ if (extract32(ctx->opcode, 2, 1) == 0) {
+ generate_exception_end(ctx, EXCP_SYSCALL);
+ } else {
+ generate_exception_end(ctx, EXCP_RI);
+ }
+ break;
+ case NM_BREAK16:
+ generate_exception_end(ctx, EXCP_BREAK);
+ break;
+ case NM_SDBBP16:
+ if (is_uhi(extract32(ctx->opcode, 0, 3))) {
+ gen_helper_do_semihosting(cpu_env);
+ } else {
+ if (ctx->hflags & MIPS_HFLAG_SBRI) {
+ generate_exception_end(ctx, EXCP_RI);
+ } else {
+ generate_exception_end(ctx, EXCP_DBp);
+ }
+ }
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ }
break;
case NM_P16_SHIFT:
{
@@ -16842,6 +16876,13 @@ static int decode_nanomips_opc(CPUMIPSState *env,
DisasContext *ctx)
}
break;
case NM_LI16:
+ {
+ int imm = extract32(ctx->opcode, 0, 7);
+ imm = (imm == 0x7f ? -1 : imm);
+ if (rt != 0) {
+ tcg_gen_movi_tl(cpu_gpr[rt], imm);
+ }
+ }
break;
case NM_ANDI16:
break;
--
2.7.4
- [Qemu-devel] [PULL 27/46] target/mips: Fix pre-nanoMIPS MT ASE instructions availability control, (continued)
- [Qemu-devel] [PULL 27/46] target/mips: Fix pre-nanoMIPS MT ASE instructions availability control, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 24/46] target/mips: Add CP0 Config3 and Config5 fields to DisasContext structure, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 40/46] elf: Relax MIPS' elf_check_arch() to accept EM_NANOMIPS too, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 20/46] target/mips: Add emulation of misc nanoMIPS instructions (p_lsx), Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 22/46] target/mips: Implement emulation of nanoMIPS EXTW instruction, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 02/46] target/mips: Add nanoMIPS base instruction set opcodes, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 19/46] target/mips: Add emulation of misc nanoMIPS instructions (pool32axf), Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 43/46] mips_malta: Add basic nanoMIPS boot code for Malta board, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 35/46] target/mips: Add availability control via bit NMS, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 15/46] target/mips: Add emulation of nanoMIPS instructions MOVE.P and MOVE.PREV, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 10/46] target/mips: Add emulation of nanoMIPS 16-bit misc instructions,
Aleksandar Markovic <=
- [Qemu-devel] [PULL 05/46] target/mips: Add placeholder and invocation of decode_nanomips_opc(), Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 13/46] target/mips: Add emulation of nanoMIPS 16-bit save and restore instructions, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 11/46] target/mips: Add emulation of nanoMIPS 16-bit load and store instructions, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 08/46] target/mips: Add emulation of nanoMIPS 16-bit branch instructions, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 16/46] target/mips: Add emulation of nanoMIPS 48-bit instructions, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 21/46] target/mips: Implement emulation of nanoMIPS ROTX instruction, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 30/46] target/mips: Add emulation of DSP ASE for nanoMIPS - part 2, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 34/46] target/mips: Add emulation of DSP ASE for nanoMIPS - part 6, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 37/46] target/mips: Add updating BadInstr and BadInstrX for nanoMIPS, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 33/46] target/mips: Add emulation of DSP ASE for nanoMIPS - part 5, Aleksandar Markovic, 2018/08/21