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[Qemu-devel] [PATCH v1 7/8] s390x/tcg: fix FP register pair checks
From: |
David Hildenbrand |
Subject: |
[Qemu-devel] [PATCH v1 7/8] s390x/tcg: fix FP register pair checks |
Date: |
Wed, 22 Aug 2018 09:57:49 +0200 |
Valid register pairs are 0/2, 1/3, 4/6, 5/7, 8/10, 9/11, 12/14, 13/15.
R1/R2 always selects the lower number, so the current checks are not
correct as e.g. 2/4 could be selected as a pair.
Signed-off-by: David Hildenbrand <address@hidden>
---
target/s390x/translate.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index 1ca6ef45a1..27d2405ef4 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -1110,7 +1110,7 @@ typedef struct {
#define IF_HFP3 0x0004 /* r3 points at fp reg for HFP instructions */
#define IF_BFP 0x0008 /* binary floating point instruction */
#define IF_DFP 0x0010 /* decimal floating point instruction */
-#define IF_PRIV 0x0020 /* priviledged instruction */
+#define IF_PRIV 0x0020 /* privileged instruction */
struct DisasInsn {
unsigned opc:16;
@@ -5985,6 +5985,12 @@ static bool is_afp_reg(int reg)
return reg % 2 || reg > 6;
}
+static bool is_fp_pair(int reg)
+{
+ /* 0,1,4,5,8,9,12,13: to exclude the others, check for single bit */
+ return !(reg & 0x2);
+}
+
static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s)
{
const DisasInsn *insn;
@@ -6013,7 +6019,7 @@ static DisasJumpType translate_one(CPUS390XState *env,
DisasContext *s)
/* process flags */
if (insn->flags) {
- /* priviledged instruction */
+ /* privileged instruction */
if ((s->base.tb->flags & FLAG_MASK_PSTATE) && (insn->flags & IF_PRIV))
{
gen_program_exception(s, PGM_PRIVILEGED);
return DISAS_NORETURN;
@@ -6067,17 +6073,11 @@ static DisasJumpType translate_one(CPUS390XState *env,
DisasContext *s)
excp = PGM_SPECIFICATION;
}
}
- if (spec & SPEC_r1_f128) {
- r = get_field(&f, r1);
- if (r > 13) {
- excp = PGM_SPECIFICATION;
- }
+ if ((spec & SPEC_r1_f128) && !is_fp_pair(get_field(&f, r1))) {
+ excp = PGM_SPECIFICATION;
}
- if (spec & SPEC_r2_f128) {
- r = get_field(&f, r2);
- if (r > 13) {
- excp = PGM_SPECIFICATION;
- }
+ if ((spec & SPEC_r2_f128) && !is_fp_pair(get_field(&f, r2))) {
+ excp = PGM_SPECIFICATION;
}
if (excp) {
gen_program_exception(s, excp);
--
2.17.1
- [Qemu-devel] [PATCH v1 0/8] s390x/tcg: instruction flags and AFP registers, David Hildenbrand, 2018/08/22
- [Qemu-devel] [PATCH v1 7/8] s390x/tcg: fix FP register pair checks,
David Hildenbrand <=
- [Qemu-devel] [PATCH v1 8/8] s390x/tcg: refactor specification checking, David Hildenbrand, 2018/08/22
- [Qemu-devel] [PATCH v1 6/8] s390x/tcg: handle privileged instructions via flags, David Hildenbrand, 2018/08/22
- [Qemu-devel] [PATCH v1 5/8] s390x/tcg: check for AFP-register, BFP and DFP data exceptions, David Hildenbrand, 2018/08/22
- [Qemu-devel] [PATCH v1 3/8] s390x/tcg: support flags for instructions, David Hildenbrand, 2018/08/22
- [Qemu-devel] [PATCH v1 2/8] s390x/tcg: store in the TB flags if AFP is enabled, David Hildenbrand, 2018/08/22
- [Qemu-devel] [PATCH v1 1/8] s390x/tcg: factor out and fix DATA exception injection, David Hildenbrand, 2018/08/22