[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] [Question] Question about the i440FX device
|
From: |
Paolo Bonzini |
|
Subject: |
Re: [Qemu-devel] [Question] Question about the i440FX device |
|
Date: |
Mon, 10 Sep 2018 01:11:33 +0200 |
|
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 |
On 07/09/2018 08:32, Li Qiang wrote:
> Hello all,
>
> I want to know why the i440FX in the following 'info qtree' information is
> laid under the pci.0 bus. In the chip spec here:
> -->https://wiki.qemu.org/images/b/bb/29054901.pdf
> I don't see this device.
>
> Can anyone give me some hints?
Hi,
the device implements what is in "3.2. PCI Configuration Space Mapped
Registers" in the i440FX spec.
Paolo